TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 14

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

3
3.1
3.2
3.3
3.4
Processor Core
core). For information on the operations of this processor core, please refer to the “Cortex-M3
Technical Reference Manual” issued by ARM Limited. This chapter describes the functions unique to
the TX03 series that are not explained in that document.
information on each revision, see the documents issued by ARM Limited.
Processor Core
Optional block
Event
SLEEPDEEP
The TX03 series has a high-performance 32-bit processor core (the ARM Cortex-M3 processor
The following table shows the revision of the processor core in the TMPM370FY. For further
The Cortex-M3 core has the optional blocks. The optional blocks of the revision r2p0 are below;
TMPM370FY is not support event input/output. Do not use SEV instruction and WFE instruction.
TMPM370FY is not support SLEEPDEEP. Do not set SLEEPDEEP bit.
Event signal is not supported also. Do not use WFE instruction.
O: Implement
X: Not implement
Product Name
Optional block
FPB
DWT
ITM
MPU
ETM
AHB-AP
AHB trace macro-cell interface
TPIU
WIC
TMPM370FY
TM
TMPM370 3-1
Core Revision
Implementation
r2p0
O
O
O
O
O
O
O
X
X
Processor Core
TMPM370