TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 225

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

11.2 Outline
11.2.1 Interrupt Mode (WDMOD<RESCR>=0)
11.2.2 Reset Mode (WDMOD<RESCR>=1)
WDT counter
NMI
WDT clear
The watchdog timer consists of the binary counters that are arranged in 25 stages and work using the
f
2
when an overflow occurs, as shown in Fig. 11-2.
When an overflow occurs, resetting the chip itself is an option to choose. If the chip is reset, a reset is
affected for a 32-state time, as shown in Fig. 11-3. If this reset is affected, the clock f
gear generates by dividing the clock f
WDT counter
NMI
Internal reset
SYS
21
, 2
When an overflow occurs, the watchdog timer generates NMI to the CPU.
system clock as an input clock. The outputs produced by these binary counters are 2
23
are 2
25
.By selecting one of these outputs with WDMOD <WDTP2:0>, NMI can be generated
n
n
Overflow
(3.2 μs @ fosc = 10 MHz, f
Fig. 11-2 Interrupt Mode
Fig. 11-3 Reset Mode
TMPM370 11-2
C
of the high-speed oscillator by 1 is used as an input clock f
Overflow
32-state
Write of a clear code
C
= fsys = 10 MHz,)
Watchdog Timer
SYS
0
that the clock
TMPM370
15
, 2
17
, 2
SYS
19
,
.