TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 19

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

5
The internal ROM, internal RAM and internal I/O regions of the TMPM370FY are mapped to the code,
SRAM and peripheral regions of the Cortex-M3 respectively. The SRAM and internal I/O regions are all
included in the bit-band region.
hard fault is generated if memory fault is disable. Do not access the vendor-specific regions.
Memory Map
The memory maps for the TMPM370FY are based on the ARM Cortex-M3 processor core memory map.
The CPU register region is the processor core’s internal register region.
For more information on each region, see the “Cortex-M3 Technical Reference Manual”.
Note that regions indicated as “Fault” is accessed, memory fault is generated if memory fault is enable, or
See “Special Function Registers” for details on the internal I/O region.
TMPM370 5-1
Memory map
TMPM370