TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 48
TMPM370FYFG
Manufacturer Part Number
TMPM370FYFG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM370FYFG.pdf
(498 pages)
Specifications of TMPM370FYFG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA
Quantity:
1 000
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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7.2 Reset Exceptions
7.3 Non-Maskable Interrupts (NMIs)
Reset Control Register.
Reset exceptions are generated from the following six sources.
Use the Reset Flag (RSTFLG) Register of the Clock Generator to identify the source of a reset.
・External reset pin
A reset exception occurs when an external reset pin changes from “Low” to “High”.
At least 12 Low level system clock is necessary for reset the device, with the condition that the power
supply is within the operation voltage and high frequency oscilation is stable.
Please refer the “Electrical characteristics” for detail about power supply sequence.
・Reset exception by POR
Please refer the chapter “POR Power on Reset circuit” for detail.
・Reset exception by VLTD
Please refer the chapter “VLTD Voltage Detection Circuit” for detail.
・Reset exception by OFD
Please refer the chapter “OFD Oscillation Frequency Detector” for detail.
・Reset exception by WDT
The watchdog timer (WDT) has a reset generating feature. For details, see the chapter on the WDT.
・Reset exception by SYSRESETREQ
A reset can be generated by setting the SYSRESETREQ bit in the NVIC’s Application Interrupt and
the chapter on the WDT.
The watchdog timer (WDT) has a non-maskable interrupt generating feature. For details, see
TMPM370 7-10
TMPM370
Interrupt
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