TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 206

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

SC0FCNF
<RFST>:
<TFIE>:
<RFIE>:
<RXTXCNT>:
<CNFG>:
(Note1)
(Note2)
10.4.8
bit Symbol
Read/Write
After reset
Function
Regarding TX FIFO, the maximum number of bytes being configured is always
available. The available number of bytes is the bytes already written to the TX FIFO.
FIFO cannot be used in the 9bit UART mode.
FIFO configuration register
When RX FIFO is enabled, the number of RX FIFO bytes to be used is selected
note)
0: The maximum number of bytes of the FIFO configured (see also <CNFG>).
1: Same as the fill level for receive interrupt generation specified by SC0RFC <RIL1:0>.
When TX FIFO is enabled, transmit interrupts are enabled or disabled by this parameter.
When RX FIFO is enabled, receive interrupts are enabled or disabled by this parameter.
Enables FIFO.
If enabled, the SCOMOD1 <FDPX1:0> setting automatically configures FIFO as follows:
(The type of TX/RX can be specified in the mode control register 1
SC0MOD1<FDPX1:0>).
Half duplex
RX
Half duplex
TX
Full duplex
Be sure to write “000”.
Controls automatic disabling of transmission and reception.
The mode control register SCOMOD1 <FDPX1:0> is used to set the types of TX/RX.
Setting “1” enables to operate as follows.
Reserved
Half duplex
RX
Half duplex
TX
Full duplex
.
7
0
Reserved
RX FIFO 4byte
TX FIFO 4byte
RX FIFO 2byte＋TX FI O 2byte
6
0
When the receive shift register, receive buffer and RX FIFO are filled
up to the specified number of valid bytes, SC0MOD0<RXE> is
automatically set to “0” to inhibit further reception.
When the data transfer in the TX FIFO, the transmit buffer and the
transmit
automatically set to “0” to inhibit further transmission.
When either of the above two conditions is satisfied, TXE/RXE are
automatically set to “0” to inhibit further transmission and
reception.
TMPM370 10-35
Reserved
5
0
shift
Bytes used
0: Maximum
1:Same as
FILL level of
RX FIFO
in RX FIFO
register
RFST
4
0
R/W
TX interrupt
for TX FIFO
0: Disabled
1: Enabled
is
TFIE
3
0
completed,
RX interrupt
for RX FIFO
0:Disabled
1: Enabled
RFIE
2
0
SC0MOD1<TXE>
1:Auto
Automatic
disable of
RXE/TXE
0:None
RXTXCNT
disable
1
0
Serial Channel
TMPM370
FIFO
enable
0: Disabled
1: Enabled
CNFG
0
0
(see
is