TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 244

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

15.2.1
PWM interrupt
ADC interrupt
VE interrupt
The ADC unit A registers ADAREG0, ADAREG1, ADAREG2, ADAREG3 and UVWISx0, UVWISx1,
UVWISx2, UVWISx3 which are the phase information specified by ADAPSETx are read into the Vector
Engine as the Vector Engine registers VEADREG0A, VEADREG1A, VEADREG2A, VEADREG3A,
VEPHNUM0A, VEPNNUM1A, VEPHNUM2A and VEPHNUM3A respectively. (These registers cannot be
accessed from the CPU.) Likewise, the ADC unit B registers are read into the Vector Engine as the Vector
Engine registers VEADREG0B, VEADREG1B, VEADREG2B, VEADREG3B, VEPHNUM0B, VEPNNUM1B,
VEPHNUM2B and VEPHNUM3B. (These registers cannot be accessed from the CPU.) These ADC
registers can be written and read from the ADC.
15.2 Configuration
and two units of AD converter (ADC). Channel 0 of the Vector Engine controls PMD channel 0, and channel
1 of the Vector Engine controls PMD channel 1.
PMD0CMPV, PMD0CMPW, PMD0MDOUT, PMD0TRGCMP0, PMD0TRGCMP1 and PMD0TRGSEL are
switched to the Vector Engine registers VECMPU0, VECMPV0, VECMPW0, VEOUTCR0, VETRGCMP00,
VETRGCMP10 and VETRGSEL0 respectively. Likewise, the PMD channel 1 registers are switched to
Vector Engine registers VECMPU1, VECMPV1, VECMPW1, VEOUTCR1, VETRGCMP01, VETRGCMP11
and VETRGSEL1. In this case, these registers can only be controlled from the Vector Engine, and cannot
be written from the PMD. Other PMD registers have no read/write restrictions.
Figure 15-2 shows the configuration of the Vector Engine.
The Vector Engine can control two motors by interacting with two channels of motor control circuit (PMD)
As shown in Figure 15-3, the Vector Engine allows direct interaction with the PMD and ADC.
When the PMD0MODESEL register is set to the VE mode, the PMD channel 0 registers PMD0CMPU,
Interaction among Vector Engine, Motor Control Circuit and A/D Converter
Schedule management
Interrupt control
Schedule control
Error detection
Start control
Figure 15-2 Configuration of the Vector Engine
Schedule 0
Schedule 1
Schedule 9
Scheduler
TMPM370 15-3
・
・
・
Input processing
Current control
Output voltage
Output control
Input voltage
conversion
conversion
generation
Trigger
Tasks
Decoder
Vector Engine (VE)
Computation unit
ADC
Registers
TMPM370
PMD
(x = 0 to 5)