TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 384

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

(1) When <P3EN> = 1 (<EN0INT> = 0x0002)
(2) When <P3EN> = 0 (<EN0INT> = 0x0002)
Capture Register, EN0CNT
Revolution Error, REVERR
Capture Register, EN0CNT
Encoder Pulse, ENCLK
19.3.1.3 Sensor Timer Count Mode
Revolution Error, REVERR
Encoder Pulse, ENCLK
Encoder Counter
Encoder Counter
・ When <ENCLR> is set to 1, causing the internal counter to be cleared to 0.
Interrupt, INTENC0
Interrupt, INTENC0
・ In Sensor Timer Count mode, the Hall sensor inputs of the TMPM370 should be connected to the
・ The encoder counter always counts up; it is cleared to 0 on ENCLK. When the encoder counter
Rotation Direction
Rotation Direction
Encoder Input, W
Encoder Input, W
Encoder Input, U
Encoder Input, V
Encoder Input, U
Encoder Input, V
・
・
・
・
(÷2) TIMPLS
(÷2) TIMPLS
around to 0xFFFF on the next ENCLK.
U, V and W channels. The encoder counter measures the interval between two contiguous
pulses of ENCLK, which is either multiplied_by_4 clock (when <P3EN> = 0) derived from the
decoded U and V signals or multiplied_by_6 clock (when <P3EN> = 1) derived from the decoded
U, V and W signals.
has reached 0xFFFFFF, it wraps around to 0.
<UD> is set to 1 during CW rotation and cleared to 0 during CCW rotation.
TIMPLS, which is derived by dividing ENCLK by a programmed factor, can be driven out
externally.
If <CMPEN> is set to 1, an interrupt is generated when the value of the internal counter has
reached the value of <EN0INT>.
Clearing <ENRUN> to 0 clears <UD> to 0.
fsys
fsys
dir
dir
1
1
0 (ini)
0 (ini)
2
2
3
3
0
0
1
1
2
2
3
3
0
0
3
3
1
1
CW
CW
TMPM370 19-15
2
2
3
3
0
0
1
1
2
2
3
3
2
2
3
3
3
3
0
0
1
1
2
2
0
0
１
１
2
2
2
2
3
3
0
0
Encoder Input Circuit
１
１
CCW
CCW
2
2
3
3
0
3
0
3
１
１
2
2
TMPM370
3
3
0
0
１
１
2
2