TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 209

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

SC0RST
SC0TST
<ROR>:
<RLVL2:0>:
(Note)
<TUR>:
<TLVL2:0>:
(Note)
10.4.11 RX FIFO status register
10.4.12 TX FIFO status register
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Function
Function
The <ROR> bit is cleared to “0” when receive data is read from the SC0BUF
The <TUR> bit is cleared to “0” when transmit data is written to the SC0BUF
register.
register.
Flags for RX FIFO overrun. When the overrun occurs, these bits are set to “1”
Flags for TX FIFO underrun. When the underrun occurs, these bits are set to “1”
note).
Shows the fill level of TX FIFO.
Shows the fill level of RX FIFO.
RX FIFO
Overrun
1:
Generated
TX FIFO
Under run
1:Generated
Cleared by
writing FIFO
ROR
TUR
7
R
0
7
R
1
“0” is read.
“0” is read.
6
6
TMPM370 10-38
5
5
R
0
R
0
4
4
3
3
Status of RX FIFO fill level
000:Empty
001:1Byte
010:2Byte
011:3Byte
100:4Byte
Status of TX FIFO fill level
000:Empty
001:1Byte
010:2Byte
011:3Byte
100:4Byte
RLVL2
TLVL2
2
0
2
0
RLVL1
TLVL1
R
1
0
１
R
0
Serial Channel
RLVL0
TLVL0
TMPM370
(see note).
0
0
0
0
(see