TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 313

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

<TRGCMP0-3>: Trigger output compare registers
Read/Write
Read/Write
Read/Write
Read/Write
000:Trigger output disabled
001:Trigger output on down-count match
010:Trigger output on up-count match
011:Trigger output on up-/down-count match
100:Trigger output at PWM carrier peak
101:Trigger output at PWM carrier bottom
110:Trigger output at PWM carrier peak/bottom
111:Trigger output disabled
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
After reset
After reset
After reset
After reset
When TRGCMPx is read, the value in the first buffer of the double buffers (data set via the bus) is
returned.
Update Timing of the Trigger Compare Register (TRGCMPx)
TRGCMPx is loaded to the second buffer depends on the setting of TRGCR<TRGxMD>. When
TRGCR<TRGxBE> is set to 1, data written to TRGCMPx is immediately loaded to the second buffer.
The Trigger Compare Register (TRGCMPx) is double-buffered. The timing at which the data written to
When the PMD counter value (MDCNT) matches the value set in TRGCMPx, PMDTRG is output.
TRGCMPx should be set in a range of 1 to [MDPRD set value – 1].
* To load the data in TRGCMP0 and TRGCMP1 to the second buffers, select the bus mode (default)
* Do not write to these registers in byte units. If the upper 8 bits [15:8] and the lower 8 bits [7:0] are
* When TRGCMPx is set to 0x0001, no trigger output is made only in the first cycle after PWM
* It is prohibited to set TRGCMPx to 0 or the MDPRD value.
start (MDEN<PWMEN>1).
by setting MODESEL<MDSEL> to 0.
written separately, operation cannot be guaranteed.
Table 16-6 TRGCMPx Buffer Update Timing according to Trigger Output Mode Setting
R → 0
R → 0
31
23
15
0
0
0
7
0
-
-
TRGxMD
PMD0 (0x4005 0454-0458) , PMD1 (0x4005 04D4-04D7)
R → 0
R → 0
30
22
14
0
0
0
6
0
-
-
R → 0
R → 0
29
21
13
0
0
0
5
0
-
-
TMPM370 16-29
Always updated
Updated when PWM counter equals MDPRD (PWM carrier peak)
Updated when PWM counter equals 1 (PWM carrier bottom)
Updated when PWM counter equals 1 or MDPRD
Always updated
(PWM carrier peak/bottom)
R → 0
R → 0
28
20
12
0
0
0
4
0
-
-
TRGCMP3
TRGCMP3
R/W
R/W
R → 0
R → 0
27
19
11
TBUFx Update Timing
0
0
0
3
0
-
-
R → 0
R → 0
26
18
10
0
0
0
2
0
-
-
Motor control circuit
R → 0
R → 0
25
17
0
0
9
0
1
0
-
-
R → 0
R → 0
TMPM370
24
16
0
0
8
0
0
0
-
-