TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 163

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

9.5.3
9.5.4
Timer registers (TB0RG0, TB0RG1)
Capture Control
two registers are built into each channel. If the comparator detects a match between a value set
in this timer register and that in a UC up-counter, it outputs the match detection signal.
register buffers. The double buffering is disabled in the initial state.
<TBWBF> is set to “0”, the double buffering becomes disabled. If the <TBWBF> is set to “0”, it
becomes enabled. When the double buffering is enabled, a data transfer from the register buffer
to the timer register (Tb0RG0/1) is done in the case that UC is matched with TB0RG1. When the
counter is stopped even if the double buffering is enabled, the double buffering operates as a
single buffer, and an immediate data can be written to the TB0RG0 and TB0RG1.
<TB0WBF> is set to “0,” the same value is written to TB0RG0, TB0RG1 and each register buffer;
if the <TB0WBF> is set to “1,” the value is only written to each register buffer. Therefore, in order
to write an initial value to the timer register, the register buffers must be set to “disable”. Then set
<TB0WBF> = “1”and write the following data to the register.
TB0CP1 capture registers. The timing to latch data is specified by TB0MOD <TB0CPM1:0>.
specifically, UC values are taken into the TB0CP0 capture register each time “0” is written to
TB0MOD<TB0CP0>.
(TB0RUN<TB0PRUN> = “1”).
TB0RG0 and TB0RG1 are registers for setting values to compare with up-counter values and
TB0RG0 andTB0RG1 consist of the double-buffered configuration which is paired with
Controlling double buffering disable or enable is specified by TB0CR<TBWBF> bit. If the
TB0RG0/ TB0RG1 and the register buffers are assigned to the same address. If the
This is a circuit that controls the timing to latch UC up-counter values into the TB0CP0 and
Software can also be used to capture values from the UC up-counter into the capture register;
•
Interrupt
INTTB00 is generated by UC count value matching with TB0RG0 value.
INTTB01 is generated by UC count value matching with TB0RG1 value.
To
use
TMPM370 9-20
this
capability,
the
prescaler
16-bit Timer/Event Counters
must
be
TMPM370
running