TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 226

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

11.3 Control Registers
11.3.1 Watchdog Timer Mode Register (WDMOD)
11.3.2 Watchdog Timer Control Register (WDCR)
The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
1. Enabling/disabling the watchdog timer <WDTE>
2. Specifying the detection time of the watchdog timer <WDTP2: 0>
3. Enabling/disabling the watchdog timer in IDLE mode <I2WDT>
4. Watchdog timer out reset connection <RESCR>
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Enabling/disabling the watchdog timer in IDLE mode is controlled by this bit. Writing “1” to this bit
enables the watchdog timer and writing “0” to this bit disables the watchdog timer in IDLE mode.
When resetting, WDMOD <WDTE> is initialized to "1" and the watchdog timer is enabled.
To disable the watchdog timer, this bit must be set to "0" and, at the same time, the disable code
(0xB1) must be written to the WDCR register. This dual setting is intended to minimize the
probability that the watchdog timer may inadvertently be disabled if a runaway occurs.
To change the status of the watchdog timer from "disable" to "enable," set the <WDTE> bit to "1".
This is a 3-bit register for specifying the NMI time for runaway detection. When a reset is effected,
this register is initialized to WDMOD <WDTP2: 0> = "000." Fig. 11-4 shows the detection time of
the watchdog timer.
Setting this bit to "1" enables the watch dog timer to be reset when a runaway is detected. Since a
reset initializes this bit to "1," a counter overflow causes a reset.
This is a register for disabling the watchdog timer function and controlling the clearing function of
the binary counter.
By writing the disable code (0xB1) to this WDCR register after setting WDMOD <WDTE> to "0," the
watchdog timer can be disabled.
Set WDMOD <WDTE> to "1".
Writing the clear code (0x4E) to the WDCR register clears the binary counter and allows it to
resume counting.
Disabling control
Enabling control
Watchdog timer clearing control
(Note) The watchdog timer is halted in STOP mode.
(Note) Writing the disable code (0xB1) clears the binary counter.
WDMOD
WDCR
WDCR
← 0
← 1 0 1 1 0 0 0 1
← 0 1 0 0 1 1 1 0
− − − − − − −
TMPM370 11-3
Clears WDTE to "0."
Writes the disable code (0xB1).
Writes the clear code (0x4E)
Watchdog Timer
TMPM370