TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 363

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

17.6.2 Simultaneous Conversion Using One PMD (Three Shunts) and Two ADCs
ADCs.
ADC A
ADC B
PMD Trigger Program Register ADAPSETn0 and ADBPSETn0. “U”, “V” and “W” indicate the
phases of a motor. AIN inputs are selected to obtain these phases.
conversion based on reg0, and the interrupt signals (INTADAPDA , INTADBPDA) are output to
ADC A and ADC B.
Program
Program
The following shows a block diagram for AD conversion using one PMD for three shunts and two
Example ADC settings are shown below.
Programs 0 to 2 are assigned to three trigger inputs to ADC A and ADC B. “reg0” indicates the
When a trigger input occurs, ADC A and ADC B are started simultaneously to perform AD
reg0
reg0
INT
INT
W
U
V
U
A
V
A
0
0
AINB0
AINB1
AINB2
AINA0
AINA1
AINA2
W
V
A
A
1
1
ADC A
ADC B
W
A
U
A
2
2
TMPM370 17-47
PMD0TRGn
(n = 0～2)
3
3
PMD0TRGn
(n = 0～2)
PMD 0
INTADAPDA
INTADBPDA
Analog/ Digital Converter
TMPM370