TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 441

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

5) Automatic erasing of protection bits
Different results will be obtained when the automatic protection bit erase command is
executed depending on the status of the protection bits and the security bits. It depends on
the status of FCFLCS <BLPRO> whether all the <BLPRO> bits are set to "1" or not if
FCSECBIT<SECBIT> is 0x1. Be sure to check the value of FCFLCS <BLPRO> before
executing the automatic protection bit erase command. See chapter 17 for details.
・When all the FCFLCS <BLPRO> bits are set to "1" (all the protection bits are
programmed):
・When the FCFLCS <BLPRO> bits include "0" (not all the protection bits are
programmed):
The protection condition can be canceled by the automatic protection bit erase operation.
With this device, protection bits set by an individual block can be erased handling all the
blocks at a time as shown in Table 20-21. The target bits are specified in the seventh bus
write cycle and when the command is completed, the device is in a condition all the blocks
are erased. The protection status of each block can be checked by FCFLCS <BLPRO> to
be described later. This status of the programming operation for automatic protection bits
can be checked by monitoring FCFLCS <RDY/BSY>. When the automatic operation to
erase protection bits is normally terminated, the protection bits of FCFLCS <BLPRO>
selected for erasure are set to "0."
In any case, any new command sequence is not accepted while it is in an automatic
operation to erase protection bits. If it is desired to stop the operation, use the hardware
reset function. When the automatic operation to erase protection bits is normally terminated,
it returns to the read mode.
When the automatic protection bit erase command is command written, the flash memory is
automatically initialized within the device. When the seventh bus write cycle is completed,
the entire area of the flash memory data cells is erased and then the protection bits are
erased. This operation can be checked by monitoring FCFLCS <RDY/BSY>. If the
automatic operation to erase protection bits is normally terminated, FCFLCS will be set to
"0x00000001." While no automatic verify operation is performed internally to the device, be
sure to read the data to confirm that it has been correctly erased. For returning to the read
mode while the automatic operation after the seventh bus cycle is in progress, it is
necessary to use the hardware reset to reset the device. If this is done, it is necessary to
check the status of protection bits by FCFLCS <BLPRO> after retuning to the read mode
and perform either the automatic protection bit erase, automatic chip erase, or automatic
block erase operation, as appropriate.
(Note) The FLCS <RDY/BSY> bit is "0" while in automatic operation and it
turns to "1" when the automatic operation is terminated.
TMPM370 20-49
Flash Memory Operation
TMPM370