TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 233

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

12.3 Function
External RESET
input
Internal RESET
Oscillation Frequency
Detector control
High-frequency
clock
12.3.1
Table 12-1 Availability of oscillation frequency detector
RESET by internal reset (Note 1)
RESET by oscillation frequency
(Including warming up period)
Note 4: Specify an appropriate value to OFDMNPLLON and OFDMXPLLON depending on the clock frequency to be used under
Note 5: OFDMNPLLOFF, OFDMNPLLON, OFDMXPLLOFF and OFDMXPLLON are not initialized by an internal factor reset
Note 6: OFDMNPLLOFF/OFDMXPLLOFF and OFDMNPLLON/OFDMXPLLON are automatically switched over by the setting of
Note 1: Internal reset; Watchdog timer reset, SYSRESETREQ reset
RESET by external reset
VDD
writing "0x00" to OFDCR2 with OFDCR1="0xF9" disables the oscillation frequency detection.
writing to OFDCR2. Reading from OFDCR2 is always enabled without setting of OFDCR1. OFDCR1
is initialized to "0x06" by external reset and OFDCR2 is initialized to "0x00" by external reset. How-
ever, OFDCR1 and OFDCR2 are not initialized by internal reset which are SYSRESETREQ reset,
watchdog timer reset and oscillation frequency detection reset.
matically disabled. After releasing STOP and warming up period, the oscillation frequency detection
is enabled. The oscillation frequency detection is available only in NORMAL and IDLE mode. Table
12-1 shows the availability of oscillation frequency detector.
Operating Mode
detection reset
Enabling and Disabling the Oscillation Frequency Detection
Writing "0xE4" to OFDCR2 with OFDCR1="0xF9" enables the oscillation frequency detection, and
Setting "0xF9" to OFDCR1 enables writing to OFDCR2 and setting "0x06" to OFDCR1 disables
Note:After writing data to OFDCR2, set "0x06" to OFDCR1 to protect OFDCR2 register.
When STOP mode is executed with OFDCR2=0xE4, the oscillation frequency detection is auto-
NORMAL
the condition of OFDMNPLLON<OFDMXPLLON. For how to calculate the value, refer to " 12.3.2 Setting the Lower and
Higher Frequency for Detection ".
including oscillation frequency detection reset. To initialize these registers, set the RESET pin (external factor reset) to the
low level.
PLLON.
STOP
IDLE
Disable
External
RESET
Figure 12-3 Availability of Oscillation Frequency Detection
NORMAL or
IDLE mode
Enabling by writting
0xE4 to CLKSCR
Enable
Oscillation Frequency Detection
(OFDCR2=0xE4)
Available
Available
Available
Available
Disable
STOP mode
including warming up
Disable
TMPM370 12-5
Oscillation Frequency Detection is disabled automatically.
NORMAL or
IDLE mode
All I/Os condition after Oscillation Frequency Detection RESET
(Except power supply, RESET, X1, X2 pins)
Internal
RESET
Enable
Oscillation Frequency Detector (OFD)
NORMAL or
IDLE mode
High impedance
High impedance
High impedance
High impedance
-
External
RESET
Disable
Enable
NORMAL or
IDLE mode
Enabling by writting
0xE4 to CLKSCR
TMPM370