TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 486

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TMPM370FYFG

Manufacturer Part Number
TMPM370FYFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM370FYFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA
Quantity:
1 000
Part Number:
TMPM370FYFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
24.7.1 Serial Channel Timing (SIO)
SCLK Clock High width (input)
SCLK Clock Low width (input)
SCLK cycle
In case of
transfer
mode
In case of
receive
mode
SCLK cycle (programmable)
In case of
transfer
mode
In case of
receive
mode
(Note 2) t
(Note 1) SCLK rise or fall:Measured relative to the programmed active edge of SCLK.
24.7 AC Electrical Characteristics
(1) I/O Interface mode
AC measuremetn condition
(Note 1) VDD = DVDD5E = DVDD5 = AVDD5A = AVDD5B = AMPVDD5
SCLK input mode
SCLK output mode
keep t
Input levels: Refer to low-level input voltage and high-level input voltage in DC Electrical
Output levels: High 0.8VDD V/Low 0.2VDD, CL=30pF
OutputData to SCLK rise
OutputData hold after SCLK rising
InputData valid to SCLK rise
InputData hold after SCLK rising
In the table below, the letter x represents the period of the system clock (fsys). It varies depending on
the programming of the clock gear function.
oss
OutputData to SCLK rise or fall (Note 1)
OutputData hold or fall after SCLK
rising (Note 1)
Input Data valid SCLK rise or fall (Note
1)
InputData hold or fall after SCLK rising
(Note 1)
should be always positive. Therefore, set proper SCLK parameters (t
oss
Parameter
Parameter
positive. (t
Characteristics.
oss
> 0)
TMPM370 24-5
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
SCH
OSS
OHS
SRD
HSR
OSS
OHS
SRD
HSR
SCL
SCY
SCY
t
SCY
t
t
scy
scy
t
/2 − 4x − 45
SCH
Min.
x + 30
/2 − 20
/2 − 20
Min.
t
45
SYC
4x
0
30
3x
3x
+ t
/2
Equation
Equation
SCL
(VDD = 4.5V to 5.5V, Ta = −40 to 85°C)
(VDD = 4.5V to 5.5V, Ta = −40 to 85°C)
Max.
Max.
0 (Note 2)
Electrical Characteristics
Min.
Min.
37.5
37.5
37.5
42.5
75
30
50
45
5
5
0
80MHz
80MHz
SCY
, t
SCL
Max.
Max.
and t
TMPM370
SCY
Unit
Unit
) to
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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