TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 34

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

Not
Ports
Ports
○：
×：
6.6.1
6.6.2
(Note1)
(Note2)
Input or output enabled
Input or output disabled.
X1
X2
RESET, MODE
PB3, PB5
[When used as a debug pin
(PBFR<n>=1) and output is enabled
(PBCR<n>=1)]
PH0-2, PA0, PA2, PE4, PE6-7, PA7, PD3,
PL0-1, PJ6-7, PK0-1
[When used as an interrupt pin
(PxFR<n>=1) and input is enabled
(PxIE<n>=1)
Other port pins
IDLE mode. When the IDLE mode is entered, peripheral functions for which operation in the IDLE
mode is disabled stop operation and hold the state at that time.
see the chapter on each peripheral function.
starts operation.
shows the pin status in the STOP mode.
Only the CPU is stopped in this mode.
Each peripheral function has one bit in its control register for enabling or disabling operation in the
The following peripheral functions can be enabled or disabled in the IDLE mode. For setting details,
All the internal circuits including the internal oscillator are brought to a stop.
By releasing the STOP mode, the device returns to the preceding mode of the STOP mode and
The STOP mode enables to select the pin status by setting the CGSTBYCR<DRVE>.Table 6-3
IDLE Mode
STOP Mode
In STOP modes, the PLL is disabled. When returning from these modes, configure the
warm-up time in consideration of the stability time of the PLL. It takes approx. 200μs
for the PLL to be stabilized. When the PLL is not used, 60μs or more is needed for
warm-up to stabilize the internal circuit.
When PB4 is configured as a debug function pin, it prevents the low power
consumption mode from being fully effective. Configure PB4 to function as a
general-purpose port when the debug function is not used.
16-bit timer/event counter (TMRB)
Serial channel (SIO)
Watchdog timer (WDT)
Vector Engine (VE)
Pin Name
Table 6-3 Pin States in STOP Mode
TMPM370 6-14
Output only
Input only
Input only
Output
Output
Output
Input
Input
Input
I/O
Disabled when data is invalid.
Enabled when data is valid.
“H” level output
<DRVE>=0
×
○
×
○
×
×
×
Disabled when data is invalid.
Enabled when data is valid.
Clock/Mode control
Depends on PxCR<n>.
Depends on PxCR<n>.
Depends on PxIE<n>.
Depends on PxIE<n>.
“H” level output
<DRVE>=1
○
○
×
TMPM370