TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 185

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

Receive interrupt
10.3.7
10.3.8
Receive buffer2
Receive buffer1
RX FIFO
The following example describes the case a 6-byte data stream is received in the half duplex
mode:
SC0MOD1<6:5>=01: Transfer mode is set to half duplex mode.
SC0FCNF <4:0>=10111: Automatically inhibits continued reception after reaching the fill level.
SC0RFC<1:0>=00: Sets the interrupt to be generated at fill level 4.
SC0RFC<7:6>=11: Clears receive FIFO and sets the condition of interrupt generation.
In this condition, data reception may be initiated by setting the half duplex transmission mode
and writing “1” to the RXE bit. When the data is stored all in the receive shift register, receive
buffer and receive FIFO, SCxMOD0<RXE>
operation is finished.
RBFLL
setting the wake-up function SC0MOD0 <WU> to “1.” In this case, the interrupt INTRX0 will
be generated only when SC0CR <RB8> is set to “1.”
In addition to the double buffer function already described, data may be stored using the
receive FIFO buffer. By setting <CNFG> of the SC0FCNF register and <FDPX1:0> of the
SC0MOD1 register, the 4-byte(maximum) receive buffer can be enabled. Also, in the UART
mode or I/O interface mode, data may be stored up to a predefined fill level. When the
receive FIFO buffer is to be used, be sure to enable the double buffer function.
If data with parity bit is to be received in the UART mode, parity check must be performed
each time a data frame is received.
I/O interface mode with SCLK output:
Receive FIFO Buffer
Receive FIFO Operation
RXE
1 byte
Fig. 10-3 Receive FIFO Operation
The number of bytes to be used in the receive FIFO is the same as
the interrupt generation fill level.
2 byte
1 byte
TMPM370 10-14
1 byte
3 byte
2 byte
2 byte
1 byte
4 byte
3 byte
is automatically cleared and the receive
3 byte
2 byte
1 byte
5 byte
4 byte
4 byte
3 byte
2 byte
1 byte
6 byte
5 byte
4 byte
3 byte
2 byte
1 byte
Serial Channel
TMPM370
5 byte
4 byte
3 byte
2 byte
1 byte