AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet

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... Freescale Semiconductor, Inc. Application Note AN2468 Rev. 0, 12/2003 Understanding the MPC7450 Family L3 Cache Hardware Interface Michael Everman This document covers many of the issues that arise when designing the backside cache for CPD Applications members of the MPC7450 family of microprocessors. Because many other resources discussing general hardware design are available, this application note will focus on features or areas that are specific or new to the MPC7450 family ...

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Freescale Semiconductor, Inc. Introduction Introduction • Use ‘Y’ or ‘T’ topologies with equal stub lengths for address and control signals; ‘daisy-chains’ are not generally recommended • Do not use signal terminators unless careful simulation shows them to be necessary Because ...

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Freescale Semiconductor, Inc. MPC7457 L3_ECHO_CLK[0] {L3_DATA[0:15], {L3_DATA[16:31], L3_ECHO_CLK[1] L3_ECHO_CLK[2] {L3_DATA[32:47], {L3_DATA[48:63], L3_ECHO_CLK[3] Figure 1. Typical Signal Connections for 4M L3 Cache PB2 and Late Write SRAM Table 1. L3 Interface Signal Functions for Pipelined Burst and Late Write SRAM Signals ...

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Freescale Semiconductor, Inc. Configuring the L3 Cache Interface in Software Configuring the L3 Cache Interface in Software MPC7457 {L3DATA[0:15], {L3DATA[16:31], {L3_DATA[32:47], {L3DATA[48:63], Figure 2. Typical Signal Connections for L3 Interface with 4M DDR SRAM Table 2. L3 Interface Signal Functions ...

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Freescale Semiconductor, Inc. register, the L3 Private Memory Address Register (L3PM), used to set the base address for private memory space when the L3 cache is operating in private memory mode, but this is not of concern from a hardware ...

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Freescale Semiconductor, Inc. Configuring the L3 Cache Interface in Software Configuring the L3 Cache Interface in Software VCO_clk core_clk internal_L3clk L3CLK[0:1] L3_ADDR Address 0 L3_DATA Figure 3. Offset of L3_CLK Signals from Internal L3 Clock with 4:1 Core:L3 Ratio In ...

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Freescale Semiconductor, Inc. VCO_clk core_clk internal_L3clk L3CLK[0:1] L3_ADDR Address 0 L3_DATA Locations of L3_CLK edges if offset exactly ¾ L3CLK period from internal_L3clk Figure 5. Location of L3_CLK Edges with 3.5:1 Core:L3 Ratio and L3CR[L3NIRCA These slight deviations ...

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Freescale Semiconductor, Inc. Configuring the L3 Cache Interface in Software Configuring the L3 Cache Interface in Software Table 3. L3OH0 and L30H1 Implementations by Device L3OH0 L3OH1 (L2CR[12]) (L3CR[12]) MPC7455 Rev. 2.0 and Prior 0 0 Not supported 0 1 ...

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Freescale Semiconductor, Inc. MPC7455 L3_ECHO_CLK[0] Denotes Signals {L3_DATA[0:15], Being Latched by SRAM 0 Relative to L3_CLK[0] {L3_DATA[16:31], L3_ECHO_CLK[1] L3_ECHO_CLK[2] Denotes Signals Being Latched {L3_DATA[32:47], by SRAM 1 Relative to L3_CLK[1] {L3_DATA[48:63], L3_ECHO_CLK[3] Figure 6. Example Showing Effects of Setting L3OH[0-1] ...

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Freescale Semiconductor, Inc. Configuring the L3 Cache Interface in Software Configuring the L3 Cache Interface in Software Table 4. Read-to-Write Turn Around Time Settings MSSCR0[L3TCEN] MSSCR0[L3TC 0b00 1 0b01 1 0b10 ...

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Freescale Semiconductor, Inc. Table 5. L3OHCR Bit Field Descriptions (continued) L3OHCR Bits Bit Field Name 8-10 L3DOH0 11-13 L3DOH8 14-16 L3DOH16 17-19 L3DOH24 20-22 L3DOH32 23-25 L3DOH40 26-28 L3DOH48 29-31 L3DOH56 2.5 L3 Input Timing Control Registers (L3ITCRn) Though these ...

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Freescale Semiconductor, Inc. Clocks and Timing Clocks and Timing 3.2 Clocking and Address and Control Signals As shown in Figure 7, each SRAM latches the shared address and control signals using one of the L3_CLK[0:1] signals. It should be noted ...

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Freescale Semiconductor, Inc. Table 6. Clock Groups for Write Accesses (All SRAM Types) Signal L3_DATA[32:63] L3DP[4:7] MPC7450 L3_ECHO_CLK[0] Denotes signals {L3_DATA[0:15], driven and latched relative to L3_CLK[0] {L3_DATA[16:31], L3_ECHO_CLK[1] L3_ECHO_CLK[2] Denotes signals driven and {L3_DATA[32:47], latched relative to L3_CLK[1] {L3_DATA[48:63], ...

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Freescale Semiconductor, Inc. Clocks and Timing Clocks and Timing MPC7450 Denotes Signals {L3_DATA[0:15], Being Latched by SRAM 0 Relative to L3_CLK[0] {L3_DATA[16:31], L3_DP[2:3]} Denotes Signals Being Latched by SRAM 1 Relative to L3_CLK[1] {L3_DATA[32:47], L3_DP[4:5]} Denotes Signals {L3_DATA[48:63], Skewed by ...

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Freescale Semiconductor, Inc. does not affect L3 output AC timing in any way. See Section 4.2.1, “Adjusting AC Timing Margins for Pipelined Burst and Late Write SRAM,” for more information. When the length of the synchronization loop is the same ...

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Freescale Semiconductor, Inc. Clocks and Timing Clocks and Timing MPC7450 L3_ECHO_CLK[0] Denotes Signals Latched Relative to L3_ECHO_ CLK[0] {L3_DATA[16:31], L3_ECHO_CLK[1] L3_ECHO_CLK[2] Denotes Signals Latched Relative {L3_DATA[32:47], to L3_ECHO_ CLK[2] {L3_DATA[48:63], L3_ECHO_CLK[3] Figure 10. Data Read Clock Grouping for PB2 and ...

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Freescale Semiconductor, Inc. Table 8. Clock Groups for Read Accesses to MSUG2 DDR SRAM (continued) Signal L3_DATA[48:63] L3DP[6:7] MPC7455 Denotes Signals Latched by {L3DATA[0:15], L3_ECHO_CLK[0] {L3DATA[16:31], Denotes Signals Latched by L3_ECHO_CLK[1] Denotes Signals Latched by L3_ECHO_CLK[2] {L3_DATA[32:47], {L3DATA[48:63], Denotes Signals ...

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Freescale Semiconductor, Inc. Adjusting AC Timing Margins Adjusting AC Timing Margins 4 Adjusting AC Timing Margins After performing a careful timing analysis of the interface, it may be desirable or necessary to make adjustments to the timing. This is most ...

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Freescale Semiconductor, Inc. L3ADDR[17:0] MPC7457 L3_CNTL[0] L3_CNTL[1] L3_ECHO_CLK[0] Denotes Signals {L3DATA[0:7], Driven and Latched {L3DATA[8:15], L3DP[1]} Relative to L3_CLK[0] L3_CLK[0] {L3DATA[16:23], {L3DATA[24:31], L3DP[3]} L3_ECHO_CLK[1] {L3DATA[32:63], L3DP[4:7]} L3_ECHO_CLK[2:3] Figure 12. Example 1: Short Traces on L3_DATA[8:15] and L3_DP[1] L3_CLK[0] L3_DATA[0:7] Data ...

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Freescale Semiconductor, Inc. Adjusting AC Timing Margins Adjusting AC Timing Margins L3CLK[0] L3_DATA[0:7] Data 0 L3_DATA[8:15] Data 0 L3_DATA[16:23] Data 0 L3_DATA[24:31] Data 0 SRAM Input Setup Time Requirement Figure 14. Example 1: Input Hold Time Violation Corrected using L3OHCR[L3DOH8] ...

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Freescale Semiconductor, Inc. L3ADDR[17:0] MPC7457 L3_CNTL[0] L3_CNTL[1] L3_ECHO_CLK[0] Denotes Signals {L3DATA[0:7], Driven and Latched {L3DATA[8:15], L3DP[1]} Relative to L3_CLK[0] L3_CLK[0] {L3DATA[16:23], {L3DATA[24:31], L3DP[3]} L3_ECHO_CLK[1] {L3DATA[32:63], L3DP[4:7]} L3_ECHO_CLK[2:3] Figure 15. Example 2: Long Traces on L3_DATA[8:15] and L3_DP[1] L3CLK[0] L3_DATA[0:7] Data ...

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Freescale Semiconductor, Inc. Adjusting AC Timing Margins Adjusting AC Timing Margins L3CLK[0] L3_DATA[0:7] Data 0 L3_DATA[8:15] L3_DATA[16:23] Data 0 L3_DATA[24:31] Data 0 SRAM Input Setup Time Requirement Figure 17. Example 2: Input Setup Time Violation Corrected using L3OHCR[L3CLK0_OH] As shown ...

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Freescale Semiconductor, Inc. 4.2 Adjusting AC Timing Margins Using Hardware In situations where it is not possible to correct timing margins in software, the only other recourse is to adjust trace lengths to skew signals. Generally speaking, if the recommendations ...

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Freescale Semiconductor, Inc. Adjusting AC Timing Margins Adjusting AC Timing Margins Data Write, Address, and Control: L3 Address, Control, and Data (at SRAM) L3_CLK[0:1] (at SRAM) Making the L3_CLK signal trace shorter moves the clock edge in this direction Data ...

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Freescale Semiconductor, Inc. Table 9. Effects of Clock Trace Lengths on AC Timing Margins for PB2 and Parameter Processor input setup margin Processor input hold margin The amount the parameters will increase or decrease is determined by the amount of ...

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Freescale Semiconductor, Inc. Adjusting AC Timing Margins Adjusting AC Timing Margins 4.3.2 Adjusting Data Read Timing To affect a change in the processor’s input setup and input hold margins, the length of the corresponding L3 echo clock trace should be ...

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Freescale Semiconductor, Inc. Data Write, Address, and Control: L3 address and control (at SRAM) L3_DATA (at SRAM) L3_CLK[0:1] (at SRAM) Making the L3_CLK signal trace shorter moves the clock edge in this direction Changing the echo clock trace lengths has ...

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Freescale Semiconductor, Inc. Special Considerations for the L3 Address Bus Special Considerations for the L3 Address Bus MSUG2 DDR, the MPC7450 utilizes two-beat bursts to access that SRAM. That is, one address is issued for every two beats of data, ...

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Freescale Semiconductor, Inc. dedicated bus. While this goes beyond the original intent of the interface, such an application of the interface is possible if carefully considered and properly implemented likely that the private memory feature will be very ...

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Freescale Semiconductor, Inc. References and Revision History References and Revision History Table 12. L3 Address to Physical Address Bit Mapping (continued) Private Memory Size and Corresponding Physical Address Bit L3 Address Bit L3_ADDR[1] L3_ADDR[0] 1 Entries in parentheses indicate the ...

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Freescale Semiconductor, Inc. 6.2 Revision History Table 14 provides a revision history for this application note. Table 14. Document Revision History Table Rev. No. Date 0 12/2003 Initial release. MOTOROLA Understanding the MPC7450 Family L3 Cache Hardware Interface For More ...

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... Motorola, Inc. The PowerPC name is a trademark of IBM Corp. and is used under license. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2003 AN2468 For More Information On This Product, Go to: www.freescale.com ...