AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 18

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Adjusting AC Timing Margins
Adjusting AC Timing Margins
4 Adjusting AC Timing Margins
After performing a careful timing analysis of the interface, it may be desirable or necessary to make
adjustments to the timing. This is most easily accomplished by using the L3OH[0–1] bits (for the MPC7455)
or L3OHCR (for the MPC7457). However, there is no such software mechanism for the MPC7450.
Likewise, if the available settings do not provide the needed timing relief in an MPC7455 system, it may be
necessary to adjust the length of the traces on the routed board.
A simple approach to L3 design is as follows:
Repeat analysis and simulation to verify correct timing
4.1 Adjusting AC Timing Margins Using Software
For the MPC7455 and MPC7457, it is much better and easier to use software to adjust AC timing margins
where possible. The L3OH[0–1] bits allow software to directly adjust the AC timing of the MPC7455
interface. The effects of these bits are straightforward and conveyed directly in the L3 AC timing
specifications. See also Section 2.1.4, “L3 Output Valid Time Adjust (L3OH1)—MPC7455-Specific,” for
more information. The L3OHCR found on the MPC7457 is more sophisticated, however, and warrants a
more detailed discussion on possible uses and benefits that can be achieved.
4.1.1 Using L3OHCR
The versatility of the L3OHCR allows most address, control, and data write timing errors to be corrected in
software.
(L3OHCR)—MPC7457-Specific,” the L3OHCR can be used to adjust the timing of individual groups of
signals. The following examples illustrate how these bits can be used.
4.1.1.1 Example 1: Correcting SRAM Input Hold Time Violations
Referring to Figure 12, suppose L3_DATA[8:15] and L3_DP[1] are routed such that their trace lengths are
shorter than the other signals in that clock group. As a result, the transitions on those signals will arrive
earlier relative to the L3_CLK0 edge than the other signals in the group. This may cause an input hold time
violation at the SRAM, as shown in Figure 13. The value of L3DOH8 can be increased to delay these signals
such that they meet the SRAM’s requirements, as shown in Figure 14. Note that no other signal groups were
affected.
18
1. Follow the guidelines in Section 1.1, “General Design Guidelines.”
2. Initially assume L3_CLK traces equal in length to the average trace length of the associated
3. Perform a detailed timing analysis based on the planned layout (before fabricating the board)
4. Investigate software means (for MPC7455 and MPC7457) of adjusting timing
5. Make adjustments to the trace lengths as needed
L3_DATA signals (see Table 6). Likewise, assume L3_ECHO_CLK feedback trace lengths (for
PB2 or late write SRAM), or L3_ECHO_CLK trace lengths (for MSUG2 DDR), equal to the trace
length of the associated L3_CLK signal (see Table 7 and Table 8). This is the baseline and is
assumed in the L3 AC timing specifications
As
Understanding the MPC7450 Family L3 Cache Hardware Interface
briefly
Freescale Semiconductor, Inc.
described
For More Information On This Product,
—
MPC7457-Specific
Go to: www.freescale.com
in
Section 2.4,
“L3
Output
Hold
Control
MOTOROLA
Register