AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 3

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

1
2
1.2.2 Signals in MSUG2 DDR Mode
Figure 2 shows the typical connectivity for the L3 interface and Table 2 lists the signals used for the
MPC7450 L3 cache interface and their functions when the interface is configured in MSUG2 DDR mode.
MOTOROLA
L3_ECHO_CLK[1,3]
L3_ECHO_CLK[0,2]
MPC7457 only; MPC7450, MPC7451, and MPC7455 implement L3_ADDR[17:0], supporting up to 2 Mbytes of
SRAM. Note that the MPC7457 supports 2M of L3 cache; the remainder must be private memory.
MPC7457 only; L3_ADDR[17] is the MSB for MPC7450, MPC7451, and MPC7455.
MPC7457
L3_ADDR[18:0]
L3_DATA[0:63]
L3CLK[0:1]
L3_DP[0:7]
L3_CTRL0
L3_CTRL1
Signals
Figure 1. Typical Signal Connections for 4M L3 Cache PB2 and Late Write SRAM
Table 1. L3 Interface Signal Functions for Pipelined Burst and Late Write SRAM
Understanding the MPC7450 Family L3 Cache Hardware Interface
1
SRAM clocks
Synchronization loop clock outputs L3_SYNC_OUT[0,1]
Synchronization loop clock inputs
Chip enable
Write enable
Address bus
Data bus
Data parity (1 bit per byte lane)
Freescale Semiconductor, Inc.
L3_ECHO_CLK[2]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[3]
For More Information On This Product,
{L3_DATA[16:31],
Description
{L3_DATA[32:47],
{L3_DATA[48:63],
{L3_DATA[0:15],
Go to: www.freescale.com
L3_ADDR[18:0]
L3_CNTL[0]
L3_CNTL[1]
L3_CLK[0]
L3_CLK[1]
L3_DP[0:1]}
L3_DP[2:3]}
L3_DP[4:5]}
L3_DP[6:7]}
Each clock drives clock input of one SRAM
L3_SYNC_IN[0,1]
L3CE
L3WE
LSB: L3_ADDR[18]
MSB: L3_DATA[0], LSB: L3_DATA[63]
Used for address and data parity if address parity
enabled
Comment/Alternate Name
2
, LSB: L3_ADDR[0]
SA[18:0]
SS
SW
DQ[0:17]
K
DQ[18:36
SA[18:0]
SS
SW
DQ[0:17]
K
DQ[18:36
SRAM 0
SRAM 1
]
]
ZZ
Introduction
ZZ
G
K
G
K
GND
GND
GV
GND
GND
GV
DD
DD
/2
/2
3