AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 17

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

The effects of incorrectly routing signals and mixing clock groups will depend on the SRAM and which
clock groups are affected. Given the tighter time constraints associated with DDR data transfers, it is all the
more critical to avoid adding skew.
For example, referencing Figure 11, if the SRAM used specifies a skew between its echo clock (CQ)
outputs, then this must be subtracted from the processor’s input setup and input hold margins if
L3_DATA[15] and L3_DATA[16] are swapped at the SRAM. (This is not the case at the time of this writing
since current MSUG2 DDR SRAM data sheets do not specify any skew between CQ outputs.) Likewise,
differences in length of the L3_ECHO_CLK[0] and L3_ECHO_CLK[1] traces would also have to be
included. No signals between the L3_CLK[0] group (that is, L3_DATA[0:31], L3DP[0:3]) should ever be
mixed with signals from the L3_CLK[1] group (that is, L3_DATA[32:63], L3DP[4:7]) because the incurred
skew (t
maximum attainable frequency.
Note that t
because all echo clocks are inputs.
MOTOROLA
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[2]
L3_ECHO_CLK[3]
Denotes Signals
Denotes Signals
Denotes Signals
Denotes Signals
Latched by
Latched by
Latched by
Latched by
MPC7455
L3CSKW1
L3CSKW2
Table 8. Clock Groups for Read Accesses to MSUG2 DDR SRAM (continued)
) during write accesses could be significant in a DDR application and severely limit the
Understanding the MPC7450 Family L3 Cache Hardware Interface
has no meaning in a DDR application and need never be included in any timing analysis
Figure 11. Data Read Clock Grouping for DDR SRAM
L3_DATA[48:63]
Freescale Semiconductor, Inc.
L3DP[6:7]
For More Information On This Product,
Signal
{L3DATA[16:31],
{L3DATA[0:15],
{L3_DATA[32:47],
{L3DATA[48:63],
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[3]
L3ADDR[17:0]
L3ECHO_CLK[2]
L3_CNTL[0]
L3_CNTL[1]
L3_CLK[0]
Go to: www.freescale.com
L3_CLK[1]
L3DP[0:1]}
L3DP[2:3]}
L3DP[6:7]}
L3DP[4:5]}
Associated Echo Clock Input
L3_ECHO_CLK[3]
D[18:35]
D[0:17]
D[18:35]
B1
D[0:17]
SA[17:0]
B2
CK
CQ
CQ
SA[17:0]
B1
B2
CQ
CK
CQ
SRAM 0
SRAM 1
Clocks and Timing
LBO
LBO
CQ
CQ
CQ
CQ
CK
CK
B3
B3
G
G
GND
GND
GND
GND
GND
GND
NC
GV
NC
GV
NC
NC
DD
DD
17
/2
/2