AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 11

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

2.5 L3 Input Timing Control Registers (L3ITCRn)
Though these registers alter the input AC timing of the MPC745x family, they are intended for factory debug
use only. However, they may be useful when debugging suspected AC timing issues associated with data
read accesses. These registers are described in the application note Using the L3ITCR Registers of the
MPC7450-family L3 Cache Interface (Motorola Application Note AN2580). Note that the effects of these
registers are not characterized or tested at this time.
3 Clocks and Timing
The MPC7450 provides two output clocks, L3_CLK[0:1], that are used by the SRAM to latch the address,
control, and data signals. The L3_ECHO_CLK[0:3] signals are used by the MPC7450 to latch data driven
by the SRAM during a read access. The hardware specifications describe several important parameters,
namely different types of clock skew, that affect an AC timing analysis of the backside interface. The L3
clock output jitter information is provided so that it may be compared with the input jitter requirements of
the SRAM, but the conservative L3 AC timing specifications provided in the hardware specifications
already include the output jitter. Therefore, it does not need to be separately considered in an L3 AC timing
analysis. Because the clock signals, particularly the L3_ECHO_CLK signals, are used differently for
pipelined burst and late write SRAM when compared to MSUG2 DDR SRAM, the subject of clocking for
each technology is treated separately for each SRAM technology.
3.1 Differential Clocks
Many SRAM devices implement differential clocks while the MPC7450 implements single-ended clocks.
Most manufacturers do support single-ended clocking of their devices, however, and provide
recommendations for how the inverted clock input (K) should be terminated. For example, a particular
manufacturer may recommend that the K input be tied to V
terminated to GV
may vary from device to device and the recommendations of the manufacturer should always be followed.
MOTOROLA
L3OHCR Bits
11-13
14-16
17-19
20-22
23-25
26-28
29-31
8-10
DD
Understanding the MPC7450 Family L3 Cache Hardware Interface
Bit Field Name
/2 in the following examples, but the required termination for a particular SRAM device
L3DOH16
L3DOH24
L3DOH32
L3DOH40
L3DOH48
L3DOH56
L3DOH0
L3DOH8
Table 5. L3OHCR Bit Field Descriptions (continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
L3_DATA[16:23], L3_DP[2]
L3_DATA[24:31], L3_DP[3]
L3_DATA[32:39], L3_DP[4]
L3_DATA[40:47], L3_DP[5]
L3_DATA[48:55], L3_DP[6]
L3_DATA[56:63], L3_DP[7]
L3_DATA[8:15], L3_DP[1]
L3_DATA[0:7], L3_DP[0]
Signals Affected
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REF
Increases input hold time margin and decreases
input setup margin at SRAM during write
accesses; does not affect read access AC timing
or GV
DD
/2. These signals are shown as being
Comment
Clocks and Timing
11