AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 5

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
Configuring the L3 Cache Interface in Software
register, the L3 Private Memory Address Register (L3PM), used to set the base address for private memory
space when the L3 cache is operating in private memory mode, but this is not of concern from a hardware
design standpoint and is not discussed in this application note.
2.1 L3 Cache Control Register (L3CR)
The L3CR is the primary configuration register for the L3 cache. This section will discuss the fields which
affect the hardware aspect of the design. Fields not discussed are associated with other aspects of the design
and are detailed in the MPC7450 RISC Microprocessor Family User’s Manual and in other application
notes.
2.1.1 L3 Clock Ratio (L3CLK)
The L3 clock is derived from the processor core clock. L3CLK determines the core:L3 clock ratio. Because
the L3 clock frequency cannot be less than the system clock frequency, the minimum L3 clock frequency in
any system is the system bus frequency. Though the various device hardware specifications specify a
maximum or typical L3 clock frequency, the specifications also explain that the actual maximum frequency
is a function of the AC timing of the processor, of the SRAM, circuit loading, and board characteristics such
as layout, signal integrity, and so forth. Stable operation of the L3 at clock frequencies higher than the value
specified in the hardware specifications is possible in a well-designed, tightly-toleranced system, but the
specified value is considered a realistic, approximate limit in a typical system. Likewise, not all designs may
be able to achieve the stated maximum frequency.
2.1.2 L3 Sample Point Configuration (L3CKSP, L3PSP, and L3SPO)
Three fields, L3CKSP, L3PSP, and L3SPO, configure the sample point settings for the MPC7450 L3 cache.
These settings determine when the processor samples the FIFO to which all data read from the SRAM is
forwarded. These settings are configured entirely in software and are mentioned here only because
propagation and loading delays on the board affect them, so the delays must be known before the sample
points can be configured. For detailed information on configuring the sample point settings, see Setting the
Sample Points on the MPC7450 L3 Backside Cache (Motorola Application Note AN2182). Note that the
sample points must be configured regardless of which type of SRAM is used and whether the L3 is used in
cache mode or private memory mode.
2.1.3 L3 Non-Integer Ratio Clock Adjustment (L3NIRCA)
This field is used to adjust the phase of the L3_CLKx with respect to the address, control, and data signals
when a non-integer clock ratio (that is, 2.5:1, 3.5:1) is used. To understand the purpose of this bit, one must
understand how the L3 clock signals are generated. The address, control, and data (for writes) are driven
based on an internal L3 clock (internal_L3clk). In order to provide adequate setup and hold times at the
SRAM inputs, the MPC7450 attempts to drive the corresponding L3_CLK edge three-quarters of an L3
clock period later. The offset is generated using the VCO clock (VCO_clk), which runs at twice the
processor core clock (core_clk) frequency. It is possible to make this delay exactly three-quarters of an L3
clock period in any integer ratio mode because the ratio of VCO_clk to L3_CLK will always be a multiple
of two and L3_CLKx can be driven on a rising or falling VCO_clk edge, as shown in Figure 3; this example
shows a data write and 4:1 core:L3 ratio.
MOTOROLA
Understanding the MPC7450 Family L3 Cache Hardware Interface
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