AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 13

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

This is only true, however, when the signals are routed as shown in Figure 8, or at least such that only signals
from L3_DATA[0:31] and L3DP[0:3] (if used) are routed to SRAM 0 regardless of order. Thus, there is a
constraint on the amount of optimization that can be done during layout. For example, if L3_DATA[32:47]
and L3DP[4:5] were routed to SRAM 0 and L3_DATA[16:31] and L3DP[2:3] to SRAM 1, as shown in
Figure 9, then t
L3_DATA[16:31] relative to L3_CLK[0] while SRAM 1 is latching them relative to L3_CLK[1]; likewise,
L3_DATA[32:47] are being driven relative to L3_CLK[1] by the processor but being latched relative to
L3_CLK[0] by SRAM 0. Optimizing the data signals within a clock group is acceptable, however. For
example, there is no penalty associated with routing L3_DATA[15] to DQ[16] and L3_DATA[16] to DQ[15]
on SRAM 0. While pipelined burst SRAM is shown in the examples in the section, the above equally applies
other SRAM types.
MOTOROLA
Denotes signals
Denotes signals
latched relative
latched relative
to L3_CLK[1]
to L3_CLK[0]
MPC7450
driven and
driven and
L3CSKW1
Understanding the MPC7450 Family L3 Cache Hardware Interface
Table 6. Clock Groups for Write Accesses (All SRAM Types)
L3_DATA[32:63]
L3DP[4:7]
would affect all of those signals. This is because the MPC7450 is driving
Signal
Freescale Semiconductor, Inc.
L3_ECHO_CLK[2]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[3]
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{L3_DATA[16:31],
Figure 8. Write Data Clock Grouping
{L3_DATA[32:47],
{L3_DATA[48:63],
{L3_DATA[0:15],
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L3_ADDR[16:0]
L3_CNTL[0]
L3_CNTL[1]
L3_CLK[0]
L3_CLK[1]
Associated clock during write access
L3_DP[0:1]}
L3_DP[2:3]}
L3_DP[4:5]}
L3_DP[6:7]}
L3_CLK[1]
SA[16:0]
SS
SW
DQ[0:17]
K
DQ[18:35
SA[16:0]
SS
SW
DQ[0:17]
K
DQ[18:35
SRAM 0
SRAM 1
Clocks and Timing
]
]
ZZ
ZZ
G
G
K
K
GND
GND
GV
GND
GND
GV
DD
DD
/2
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