AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 20

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Adjusting AC Timing Margins
Adjusting AC Timing Margins
4.1.1.2 Example 2: Correcting SRAM Input Setup Time Violations
Just as L3AOH can be used to delay the address and control signals, and L3DOHn to delay the data signals,
L3CLK0_OH and L3CLK1_OH can be used to delay the L3 clock signals. The goal in doing so, however,
is not to improve SRAM input hold time margins but to instead delay the clocks relative to the other signals
in order to improve SRAM input setup time margins. Example 2, shown in Figure 15, considers the opposite
case of Example 1. Here, the trace lengths for L3_DATA[8:15] and L3_DP[1] are longer than the other
traces, causing transitions on these signals to arrive later relative to the L3_CLK0 edge than the other signals
in the group. This creates an SRAM input setup time violation, as shown in Figure 16.
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L3_DATA[16:23]
L3_DATA[24:31]
L3_DATA[8:15]
L3_DATA[0:7]
Figure 14. Example 1: Input Hold Time Violation Corrected using L3OHCR[L3DOH8]
SRAM Input Setup
Time Requirement
L3CLK[0]
Understanding the MPC7450 Family L3 Cache Hardware Interface
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SRAM Input Hold
Time Requirement
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Corrected SRAM AC
Timing Violation
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