AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 6

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Configuring the L3 Cache Interface in Software
Configuring the L3 Cache Interface in Software
In non-integer ratios, however, there are not an even number of core clocks in an L3 clock period and thus
the VCO_clk-to-L3_CLK ratio is not a multiple of two. Therefore, there is no rising or falling VCO_clk
edge at a point in time exactly three-quarters of an L3 clock period after the internal_L3clk edge. Instead,
there will be a VCO_clk edge one-quarter of a VCO period before and after the ideal point. As a result, a
decision must be made as to which VCO_clk edge will be used to drive L3CLK[0:1]. In the default state
(L3NIRCA = 0), the VCO_clk edge just after the ideal point is used, as shown in the 3.5:1 example in
Figure 4. If L3NIRCA = 1, the VCO_clk edge just before the ideal point is used, as shown in Figure 5.
6
Figure 4. Location of L3_CLK Edges with 3.5:1 Core:L3 Ratio and L3CR[L3NIRCA] = 0 (Default)
internal_L3clk
Locations of L3_CLK edges if
offset exactly ¾ L3CLK period
from internal_L3clk
internal_L3clk
L3CLK[0:1]
L3CLK[0:1]
L3_ADDR
L3_ADDR
L3_DATA
Figure 3. Offset of L3_CLK Signals from Internal L3 Clock with 4:1 Core:L3 Ratio
VCO_clk
L3_DATA
core_clk
VCO_clk
core_clk
Understanding the MPC7450 Family L3 Cache Hardware Interface
Freescale Semiconductor, Inc.
Address 0
For More Information On This Product,
Address 0
Go to: www.freescale.com
Address 1
3/4 Clock Offset
Address 1
Data 0
Data 0
Data 1
Data 1
Data 2
MOTOROLA