AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 15

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

does not affect L3 output AC timing in any way. See Section 4.2.1, “Adjusting AC Timing Margins for
Pipelined Burst and Late Write SRAM,” for more information.
When the length of the synchronization loop is the same as the associated data traces, then the input AC
timing of the L3 interface meets those published in the hardware specifications. By making this trace longer
or shorter, the clocks can be skewed, as described in Section 4.2, “Adjusting AC Timing Margins Using
Hardware.” When doing AC timing analysis, t
L3_ECHO_CLK[1] and between L3_CLK[1] and L3_ECHO_CLK[3], must be subtracted from the
processor’s input setup and input hold margins. (Note that this applies only to read transactions for pipelined
burst and late write SRAM types.) The value of t
shown in the example in Figure 9, signals should not be mixed between clock groups due to the resulting
skew (t
L3_ECHO_CLK[3]
MOTOROLA
L3_DATA[32:63]
L3_DATA[0:31]
L3CSKW1
Table 7. Clock Groups for Read Accesses to Pipelined Burst and Late Write SRAM
L3DP[0:3]
L3DP[4:7]
Signal
). Likewise, it is incorrect to connect L3_ECHO_CLK[1]
Understanding the MPC7450 Family L3 Cache Hardware Interface
to
L3_ECHO_CLK[0]
Freescale Semiconductor, Inc.
Associated Clock Synchronization Loop
For More Information On This Product,
L3_ECHO_CLK[1] to L3_ECHO_CLK[0]
L3_ECHO_CLK[3] to L3_ECHO_CLK[2]
During Read Access
Go to: www.freescale.com
.
L3CSKW2
L3CSKW2
, which describes the skew between L3_CLK[0] and
is published in the hardware specifications. As
Source of Echo Clock Output
to
L3_ECHO_CLK[2]
L3_CLK[0]
L3_CLK[1]
Clocks and Timing
and
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