AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 29

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

dedicated bus. While this goes beyond the original intent of the interface, such an application of the interface
is possible if carefully considered and properly implemented. It is likely that the private memory feature will
be very useful in such an implementation because this configures the interface in non-cache mode so that
the L3 tags are not used and accesses to private memory space never access the system bus interface. Note,
however, that the private memory space must be cacheable and the L1 data cache enabled in order for data
accesses to reach the interface. This is because cache-inhibited accesses bypass the L3 interface (including
private memory) and data accesses are treated as cache-inhibited if the L1 data cache is disabled. (For more
information, see the MPC7450 RISC Microprocessor Family User’s Manual.) Also note that private
memory is non-coherent with respect to system memory and other devices in the system must not issue
global (GBL asserted) accesses (that is, transactions to be snooped) to the private memory address range.
Failure to observe this requirement can result in private memory data being lost if the data resides in the L1
or L2 cache and a snoop hit occurs.
The first step is to use a dual-ported SRAM compatible with one of the supported SRAM types or to design
the custom logic such that it conforms to the interface protocol of one of them. If it is not possible to make
the external device exactly match the protocol of any of the supported SRAM types, it may still be possible
to choose the mode that it most closely matches and then use some of the additional configuration options
described in earlier sections, such as L3TC, to alter the configuration of the interface.
The second step is to understand the ordering of the address bits. This is provided in Table 12.
MOTOROLA
L3_ADDR[18]
L3_ADDR[17]
L3_ADDR[16]
L3_ADDR[15]
L3_ADDR[14]
L3_ADDR[13]
L3_ADDR[12]
L3_ADDR[11]
L3_ADDR[10]
L3_ADDR[9]
L3_ADDR[8]
L3_ADDR[7]
L3_ADDR[6]
L3_ADDR[5]
L3_ADDR[4]
L3_ADDR[3]
L3_ADDR[2]
L3 Address Bit
Understanding the MPC7450 Family L3 Cache Hardware Interface
3
Table 12. L3 Address to Physical Address Bit Mapping
Freescale Semiconductor, Inc.
For More Information On This Product,
Private Memory Size and Corresponding Physical Address Bit
16 (Way 2)
17 (Way 1)
18 (Way 0)
Go to: www.freescale.com
PM
1M
19
20
21
22
23
24
25
26
27
28
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5
Special Considerations for the L3 Address Bus
15 (Way 2)
16 (Way 1)
17 (Way 0)
PM
2M
18
19
20
21
22
23
24
25
26
27
28
29
30
4
4M
17
18
19
20
21
22
23
24
25
26
27
28
29
30
15
16
17
2
1
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