AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 8

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Configuring the L3 Cache Interface in Software
Configuring the L3 Cache Interface in Software
It is important to note that for the MPC7455 Rev. 2.1, each L3OH bit separately controls one L3 clock
signal. Therefore, it is recommended that both bits be cleared or both set for this revision of the MPC7455.
Setting one bit but not the other will cause only one of the clocks to be driven earlier, effectively increasing
the clock-to-clock skew between the L3 clock signals (defined as t
Microprocessor Hardware Specifications). For example, if the L3OH[0-1] = 0b01 for the L3 interface
shown in Figure 6, all signals being latched by SRAM 0 (shown in bold) will have modified AC timing,
while those being latched by SRAM 1 will not. Therefore, a separate AC timing analysis for each SRAM,
using the default processor L3 AC timing for SRAM 1 and the modified processor L3 AC timing for
SRAM 0, is necessary. This technique is useful, however, in cases where it is not possible to make the data
trace lengths for one of the SRAMs match the associated L3 clock trace length and some additional hold
time is needed for that group of signals. Care must be taken, however, because the L3 address and control
signals are vulnerable to the added clock-to-clock skew because they are shared by both SRAMs; see
Section 3.2, “Clocking and Address and Control Signals,” for more information.
For MPC7455 Rev. 3.x and later, it is not possible to introduce clock-to-clock skew in this way because the
the bits comprise a 2-bit value that selects among 4 possible values and both L3 clock signals are equally
affected by L3OH[0–1].
Unlike earlier devices that implement L2OH bits (such as the MPC755 and MPC7410), changing the output
AC timing does not impact the L3 input setup and input hold times because the L3_ECHO_CLK signals are
not affected by the settings of these bits in any way.
8
(L2CR[12])
L3OH0
0
0
1
1
(L3CR[12])
L3OH1
0
1
0
1
Understanding the MPC7450 Family L3 Cache Hardware Interface
Table 3. L3OH0 and L30H1 Implementations by Device
Rev. 2.0 and Prior
Not supported
Freescale Semiconductor, Inc.
MPC7455
For More Information On This Product,
Go to: www.freescale.com
(Not recommended)
(Not recommended)
time for all address,
time for all address,
time for all address,
time for all address,
signals latched by
signals latched by
Least output hold
Most output hold
Most output hold
Most output hold
control and data
control and data
control and data
control and data
L3_CLK1
L3_CLK0
(Default)
signals
signals
MPC7455
Rev. 2.1
Device
Most (worst)
Least (best)
output valid
output valid
time
time
L3CSKW1
Least output hold
Most output hold
Less output hold
Even less output
and data signals
and data signals
and data signals
and data signals
address, control
address, control
address, control
address, control
hold time for all
time for all
time for all
time for all
(Default)
in the MPC7455 RISC
Rev. 3.x and Later
MPC7455
MOTOROLA
valid time
valid time
(worst)
output
output
(best)
Least
Most