AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 2

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Introduction
Introduction
Because of the clocking schemes used for the backside cache interface, propagation delays do not directly
impact an AC timing analysis of any signal which is delay matched with its associated clocks. All AC timing
parameters described in the hardware specifications assume the specified signal is delay matched with the
appropriate clock signal; that is, an L3_CLK signal for data (during write accesses), address, and control
signals, or an L3_ECHO_CLK signal for data signals during read accesses. Differences in the delays
between a signal and the associated clock signal must be accounted for in the AC timing analysis and the
guidelines are intended to minimize this. These clock groups are described in the hardware specifications
and detailed discussions can be found in Section 1, “Introduction.”
Signal integrity is a primary concern when designing a fast interface. Minimizing transmission line effects
and trace loading by the placing of the SRAM in close proximity to the processor and using the shortest
possible traces will help ensure a favorable environment. If the above guidelines are followed, signal
terminators should not be necessary and are not generally recommended unless detailed signal integrity
analysis and simulation show them to be necessary. Finally, electromagnetic interference (EMI) may be also
be of concern given the fast clock rates of the L3 bus and limiting the trace lengths will help minimize
emissions.
1.2 Signals of the L3 Cache Interface
The following sections describe the uses of the L3 interface signals for each type of SRAM technology.
Except for the echo clock signals, the signal use for MSUG2 DDR is essentially identical to pipelined burst
and late write SRAM. It is important to note that the L3_ADDR bus is little-endian, whereas all others are
big-endian. This is because the PowerPC™ architecture is a big-endian architecture while most SRAM
vendors define the address signals on their devices in a little-endian manner. For convenience, the
L3_ADDR bus is defined in a little-endian format so that L3_ADDR[0] is connected to SA[0] on the
SRAM, and so on.
1.2.1 Signals in Pipelined Burst and Late Write SRAM Modes
Figure 1 shows the typical connectivity for the L3 interface and Table 1 lists the signals used for the
MPC7450 L3 cache interface and their functions when the interface is configured in pipelined burst and late
write modes.
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Use ‘Y’ or ‘T’ topologies with equal stub lengths for address and control signals; ‘daisy-chains’ are
not generally recommended
Do not use signal terminators unless careful simulation shows them to be necessary
Understanding the MPC7450 Family L3 Cache Hardware Interface
Freescale Semiconductor, Inc.
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