AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 24

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Adjusting AC Timing Margins
Adjusting AC Timing Margins
24
Figure 19. Improving Timing Margins By Adjusting the Length of Clock and Synchronization Loop
SRAM input setup margin
SRAM input hold margin
Data Write, Address, and Control:
Data Read:
L3_ECHO_CLK[0,2]
L3 Address, Control,
and Data (at SRAM)
L3_DATA
L3_CLK[0:1]
(at CPU)
(at SRAM)
(at CPU)
Table 9. Effects of Clock Trace Lengths on AC Timing Margins for PB2 and
Parameter
Understanding the MPC7450 Family L3 Cache Hardware Interface
Making the L3_CLK signal trace shorter
moves the data in this direction
Making the synchronization loop trace
shorter moves the received echo clock
edge in this direction
Making the L3_CLK signal trace shorter
moves the clock edge in this direction
Freescale Semiconductor, Inc.
For More Information On This Product,
Traces for PB2 and Late Write SRAM
Changing the synchronization loop trace length has no effect
on data write access timing or address and control timing
Go to: www.freescale.com
Change in L3_CLK Trace Length
(Relative to Other Signals in
Late Write SRAM
Decrease
Increase
Shorten
Clock Group)
Making the L3_CLK signal trace longer
moves the data in this direction
Making the synchronization loop trace
longer moves the received echo clock
edge in this direction
Lengthen
Decrease
Increase
Making the L3_CLK signal trace longer
moves the clock edge in this direction
Loop Length (Relative to Other
Change in Synchronization
Shorten
Signals in Clock Group)
None
None
MOTOROLA
Lengthen
None
None