AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 28

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Special Considerations for the L3 Address Bus
Special Considerations for the L3 Address Bus
MSUG2 DDR, the MPC7450 utilizes two-beat bursts to access that SRAM. That is, one address is issued
for every two beats of data, a cache line access requiring two such bursts to transfer all 32 bytes.
A consequence of this is that the order of the address bits is significant for DDR. With pipelined burst or
late write SRAM, the address bits can be reordered in any fashion without worry because the SRAM’s
‘sense’ of the address space has no effect on the operation of the interface and there is a 1:1 relationship
between an address and the data stored there. For example, the processor may drive address X on the L3
address bus, which in turn is interpreted as address Y by the SRAM, but this occurs without error because
the SRAM will access address Y, if the processor drives address X.
Because the burst feature must be used with DDR SRAM, however, the processor does not supply a unique
address for every beat of data. Instead, the processor supplies one address and the SRAM accesses two
addresses, the one supplied by the processor and another determined by the SRAM itself (for example, X
and X + 1). Therefore, the SRAM’s ‘sense’ of the address space becomes significant. For example, consider
the case where the L3 address bus has been reversed at the SRAM, and the connectivity is as follows:
In this situation, the address interpreted by the SRAM is the mirror image of that driven by the processor.
For example, the SRAM will interpret address 0x00550 (as driven by the processor) as address 0x0AA00.
Now consider the case where the processor accesses L3_ADDR[17:0] = 0x00000. The reversed address bits
make no difference here and the SRAM will internally access 0x00000 and 0x00001, supplying the expected
data to the processor. If the processor initiates an access to L3_ADDR[17:0] = 0x20000 some time later,
however, the SRAM will then internally access address 0x00001 because of the reversed address bits. The
problem is immediately clear: two addresses (0x00001 and 0x20000) in the processor’s “sense” of the
address space map to address 0x00001 in the SRAM’s ‘sense’ of the address space. The result will be
corrupted data or instructions, or modified data being overwritten and lost. To avoid this situation, it is
recommended to always connect the L3 address bus signals in the correct order, particularly the lowest 2 bits
(L3_ADDR[1:0]).
5.2 Address Bus Bit Ordering and Alternative Uses of the
The address driven on the L3 address bit is derived from the physical address (PA) of the access that caused
it (as opposed to the effective or virtual address). However, the ordering of the address bits with respect to
the physical is not sequential. That is, the order of some bits is changed when compared to the physical
address. This is of no particular concern in a typical application where, by nature of being a backside cache
bus, only the MPC7450 would ever access the SRAM. Therefore, the actual appearance of the address on
the L3 bus is immaterial as no device will ever need to decode it. However, some system designers have
expressed interest in using the L3 interface with dual-ported SRAM or programmable logic devices as a fast,
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Backside Cache Interface
Understanding the MPC7450 Family L3 Cache Hardware Interface
Table 11. MSUG2 DDR Address Wiring Error Example
Freescale Semiconductor, Inc.
MPC7450 Address Pin
For More Information On This Product,
L3_ADDR[17]
L3_ADDR[16]
L3_ADDR[1]
L3_ADDR[0]
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SRAM Address Pin
SA[16]
SA[17]
SA[0]
SA[1]
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MOTOROLA