AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 26

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Adjusting AC Timing Margins
Adjusting AC Timing Margins
4.3.2 Adjusting Data Read Timing
To affect a change in the processor’s input setup and input hold margins, the length of the corresponding L3
echo clock trace should be changed. Note this does not impact the input setup and input hold margins at the
SRAM.
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SRAM input setup margin
SRAM input hold margin
Processor input setup margin
Processor input hold margin
Table 10. Effects of Clock Trace Lengths on AC Timing Margins for DDR SRAM
Parameter
Understanding the MPC7450 Family L3 Cache Hardware Interface
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Change in L3_CLK Trace Length
(Relative to Other Signals in
Decrease
Increase
Shorten
None
None
Clock Group)
Lengthen
Decrease
Increase
None
None
Change in Echo Clock Trace
Decrease
Length (Relative to Other
Increase
Shorten
Signals in Clock Group)
None
None
MOTOROLA
Lengthen
Decrease
Increase
None
None