AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 4

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Configuring the L3 Cache Interface in Software
Configuring the L3 Cache Interface in Software
1
2
2 Configuring the L3 Cache Interface in Software
Two registers, the L3 Cache Control Register (L3CR) and Memory Subsystem Control Register (MSSCR0),
are primarily used to configure the L3 cache hardware interface. The L2 Cache Control Register (L2CR)
also has 1 bit (L2CR[L3OH0]) that affects the L3 cache for the MPC7455 (only). Each of these are dealt
with individually in the following sections. The MPC7457 supports an additional register, the L3 Output
Hold Control Register (L3OHCR), not found on other MPC7450 family devices. There is one additional
4
L3_ECHO_CLK[0:4]
MPC7457 only; MPC7450, MPC7451, and MPC7455 implement L3_ADDR[17:0], supporting up to 2 Mbytes of
SRAM. Note that the MPC7457 supports 2M of L3 cache; the remainder must be private memory.
MPC7457 only; L3_ADDR[17] is the MSB for MPC7450, MPC7451, and MPC7455.
L3_ADDR[18:0]
MPC7457
L3_DATA[0:63]
L3CLK[0:1]
L3_DP[0:7]
L3_CTRL0
L3_CTRL1
Signals
Table 2. L3 Interface Signal Functions for Pipelined Burst and Late Write SRAM
Figure 2. Typical Signal Connections for L3 Interface with 4M DDR SRAM
Understanding the MPC7450 Family L3 Cache Hardware Interface
1
SRAM clocks
Echo clock inputs
Chip enable
Write enable
Address bus
Data bus
Data parity (1 bit per byte lane)
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{L3DATA[16:31],
{L3DATA[0:15],
{L3_DATA[32:47],
{L3DATA[48:63],
Description
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[3]
L3ADDR[18:0]
L3ECHO_CLK[2]
L3_CNTL[0]
L3_CNTL[1]
L3_CLK[0]
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L3_CLK[1]
L3DP[0:1]}
L3DP[2:3]}
L3DP[6:7]}
L3DP[4:5]}
Each clock drives clock input of one SRAM
Inputs for clock signals driven by SRAM for read data
L3CE
L3WE
MSB: L3_ADDR[18]
MSB: L3_DATA[0], LSB: L3_DATA[63]
Used for address and data parity if address parity
enabled
Comment/Alternate Name
2
, LSB: L3_ADDR[0]
B1
B2
CQ
D[0:17]
D[18:35]
SA[18:0]
CK
CQ
SA[18:0]
B1
B2
CQ
D[0:17]
CK
D[18:35]
CQ
SRAM 0
SRAM 1
LBO
LBO
CQ
CQ
CQ
CQ
CK
CK
B3
B3
MOTOROLA
G
G
GND
GND
GND
GND
GND
GND
NC
NC
GV
NC
GV
NC
DD
DD
/2
/2