AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 30

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

References and Revision History
References and Revision History
The final step is to determine the information that will affect the software configuration, such as L3 clock
frequency, correct L3OH settings and correct sample point settings.
6 References and Revision History
6.1 References
The reference materials shown in Table 13 may be useful to the reader. Several concepts mentioned in this
application note are described in detail in these documents.
30
High-Speed Digital Design: A Handbook of Black Magic
PowerPC Backside L2 Timing Analysis for the PCB
Design Engineer
Setting the Sample Points for the MPC7450 L3 Cache
Using the L3ITCR Registers of the MPC7450-family L3
Cache Interface
1
2
3
4
5
L3_ADDR[1]
L3_ADDR[0]
Entries in parentheses indicate the function of these bits when the L3 is operated in cache mode.
These bits reflect which of the eight ways is being accessed. When operating in private memory
mode, the bits reflect the stated bits of the physical address.
MPC7457-specific; not supported on other devices. Note that because the MPC7457 does not
support 4M of L3 as cache, 4M of SRAM must be configured as either 4M of private memory or
2M of private memory and 2M of cache; see the MPC7450 RISC Microprocessor Family User’s
Manual for more information.
MPC7457-specific; not implemented on other devices.
For MPC7457 only, the value of this bit depends on the size of the SRAM and the private memory
space. For 4M of SRAM configured as 2M of cache and 2M of private memory, this bit will be
driven low (0b0) for cache accesses and high (0b1) for private memory accesses. For 2M of
SRAM configured as private memory (only), this bit is always driven low (0b0).
The value of this bit depends on the size of the SRAM and the private memory space. For 2M of
SRAM configured as 1M of cache and 1M of private memory, this bit will be driven low (0b0) for
cache accesses and high (0b1) for private memory accesses. For 1M of SRAM configured as
private memory (only), this bit is always driven low (0b0).
L3 Address Bit
Table 12. L3 Address to Physical Address Bit Mapping (continued)
Understanding the MPC7450 Family L3 Cache Hardware Interface
Title
Freescale Semiconductor, Inc.
For More Information On This Product,
Private Memory Size and Corresponding Physical Address Bit
Table 13. Reference Documentation
Go to: www.freescale.com
1M
31
32
Howard Johnson and
Martin Graham
Bruce Parker
Michael Everman
Michael Everman
Author
2M
31
32
Prentice-Hall
ISBN 0-13-395724-1
Motorola Order No. AN1794
Motorola Order No. AN2182
Motorola Order No. AN2580
4M
31
32
Document
2
MOTOROLA
1