AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 12

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Clocks and Timing
Clocks and Timing
3.2 Clocking and Address and Control Signals
As shown in Figure 7, each SRAM latches the shared address and control signals using one of the
L3_CLK[0:1] signals. It should be noted that the AC timing of the address and control signals are not
associated with one particular L3_CLK signal. Furthermore, the hardware specifications specify t
the skew between L3_CLK[0] and L3_CLK[1], also shown in Figure 7. Because the direction of this skew
is not defined, this skew must be deducted from the input setup and input hold margins for the address and
control signals of each SRAM.
3.3 Data Signals and Writes
During a write access to the SRAM, each SRAM latches one-half of the data bus (and data parity signals)
using one of the L3_CLK[0:1] signals; note that this is true regardless of which SRAM type is used. Unlike
address and control signals, however, the AC timing of each half of the data bus and the associated data
parity signals is coupled with an L3 clock signal, as shown in Table 6 and Figure 8. Therefore, t
does not affect the data signals during a write transaction.
12
Denotes Signals
Denotes Signals
Being Latched
Being Latched
MPC7450
by SRAM 1
by SRAM 0
Relative to
L3_CLK[1]
Relative to
L3_CLK[0]
Figure 7. Address and Control Signal Clocking and L3_CLK Clock-To-Clock Skew
Understanding the MPC7450 Family L3 Cache Hardware Interface
Table 6. Clock Groups for Write Accesses (All SRAM Types)
L3_DATA[0:31]
L3DP[0:3]
Signal
Freescale Semiconductor, Inc.
L3_ECHO_CLK[2]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[3]
For More Information On This Product,
{L3_DATA[16:31],
{L3_DATA[32:47],
{L3_DATA[48:63],
{L3_DATA[0:15],
Go to: www.freescale.com
L3_ADDR[16:0]
L3_CNTL[0]
L3_CNTL[1]
L3_CLK[0]
L3_CLK[1]
Associated clock during write access
L3_DP[0:1]}
L3_DP[2:3]}
L3_DP[4:5]}
L3_DP[6:7]}
t
L3CSKW1
L3_CLK[0]
SA[16:0]
SS
SW
DQ[0:17]
K
DQ[18:36
SA[16:0]
SS
SW
DQ[0:17]
K
DQ[18:36
SRAM 0
SRAM 1
]
]
ZZ
ZZ
MOTOROLA
G
G
K
K
L3CSKW1
L3CSKW1
GND
GND
GV
GND
GND
GV
DD
DD
/2
/2
,