AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 14

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Clocks and Timing
Clocks and Timing
3.4 Data Signals and Read Accesses
Aside from clocking data on rising and falling edges for DDR SRAM types, the other major difference
between the SRAM technology families from the standpoint of system design is how the processor
synchronizes data being read from the SRAM. Pipelined burst and late write are handled in the same way
and are treated together, while MSUG2 DDR is handled differently.
3.4.1 Data Signals and Reads for Pipelined Burst and Late Write SRAM
Like earlier devices, the MPC7450 uses a synchronization loop to latch data read from pipelined burst and
late write SRAM types. Unlike earlier devices that used one loop to synchronize all data being returned from
the SRAM, however, the MPC7450 implements two sync loops, one each for half of the data. The fist loop
is created by routing a trace that begins at L3_ECHO_CLK[1], runs halfway out to SRAM 0, and then back
to the L3_ECHO_CLK[0] input. The second loop begins at L3_ECHO_CLK[3], runs halfway out to
SRAM 1, and then back to the L3_ECHO_CLK[2] input. As with previous PowerPC ISA processors
featuring a backside cache interface, this allows the designer to make corrections in the AC timing budget
by adjusting the length of the loop traces. The advantage of having two loops, versus the single loop of
earlier devices, is that data returning from each SRAM is synchronized individually, allowing one to make
more refined adjustments to the timing budget of each SRAM. The disadvantage is that, as seen in the
previous example in Figure 9, fewer liberties can be taken in optimizing signal routing. Unlike earlier
devices, the MPC7450 does not employ a DLL for the L3 interface and the clock edges received at
L3_ECHO_CLK[0] and L3_ECHO_CLK[1] are used only to latch data; changing the feedback loop length
14
Denotes Signals
Denotes Signals
Denotes Signals
Being Latched
Being Latched
MPC7450
by SRAM 0
by SRAM 1
Skewed by
Relative to
L3_CLK[0]
Relative to
L3_CLK[1]
t
L3CSKW1
Figure 9. Example Showing Skew Resulting from Incorrect Signal Routing
Understanding the MPC7450 Family L3 Cache Hardware Interface
Freescale Semiconductor, Inc.
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{L3_DATA[16:31],
L3_DP[2:3]}
{L3_DATA[32:47],
L3_DP[4:5]}
{L3_DATA[48:63],
{L3_DATA[0:15],
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L3_CLK[0]
L3_CLK[1]
L3_DP[0:1]}
L3_DP[6:7]}
SA[16:0]
SS
SW
DQ[0:17]
K
DQ[18:35
SA[16:0]
SS
SW
DQ[0:17]
K
DQ[18:35
SRAM 0
SRAM 1
]
]
ZZ
ZZ
MOTOROLA
G
G
K
K
GND
GND
GV
GND
GND
GV
DD
DD
/2
/2