AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 22

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Adjusting AC Timing Margins
Adjusting AC Timing Margins
As shown in Figure 17, delaying an L3 clock has the effect of making all signal transitions appear earlier
relative to the clock. Note that care must be exercised when using L3CLKn_OH because delaying the clocks
affects the AC timing of all inputs of the SRAM receiving the clock in question (including the address and
control signals, not shown in these examples). In this case, shifting the clocks created an SRAM input hold
time violation. Fortunately, control of the output delays in L3OHCR are independent of each other.
Therefore, L3DOH0 can be used to correct the timing violation created by adjusting L3CLK0_OH, as
shown in Figure 18.
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L3_DATA[16:23]
L3_DATA[16:23]
L3_DATA[24:31]
L3_DATA[24:31]
Figure 17. Example 2: Input Setup Time Violation Corrected using L3OHCR[L3CLK0_OH]
L3_DATA[8:15]
L3_DATA[8:15]
Figure 18. Example 2: Input Setup and Hold Time Violations Corrected using L3OHCR
L3_DATA[0:7]
L3_DATA[0:7]
L3CLK[0]
L3CLK[0]
SRAM Input Setup
Time Requirement
SRAM Input Setup
Time Requirement
Understanding the MPC7450 Family L3 Cache Hardware Interface
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SRAM Input Hold
Time Requirement
SRAM Input Hold
Time Requirement
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Corrected SRAM AC
Timing Violation
Corrected SRAM AC
Timing Violation
SRAM AC Timing
Violation
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