AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 16

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Clocks and Timing
Clocks and Timing
3.4.2 Data Signals and Reads for MSUG2 DDR SRAM
While many of the concerns for pipelined burst and late write SRAM are equally applicable for address and
control signals being driven to MSUG2 DDR SRAM, and even for data signals during write transactions,
data being returned from DDR SRAM must be considered separately because of the way in which data is
being latched by the processor. Feedback loops are not used to synchronize data returning from DDR
SRAM. Instead, the SRAM itself supplies a clock that the processor uses to latch the data. Each echo clock
input is used to latch two bytes of data and associated parity, as shown in Table 8 and in Figure 11.
16
Latched Relative
Latched Relative
Denotes Signals
Denotes Signals
to L3_ECHO_
to L3_ECHO_
MPC7450
CLK[0]
CLK[2]
Figure 10. Data Read Clock Grouping for PB2 and Late Write SRAM
Understanding the MPC7450 Family L3 Cache Hardware Interface
Table 8. Clock Groups for Read Accesses to MSUG2 DDR SRAM
L3_DATA[16:31]
L3_DATA[32:47]
L3_DATA[0:15]
Freescale Semiconductor, Inc.
L3DP[0:1]
L3DP[2:3]
L3DP[4:5]
L3_ECHO_CLK[2]
L3_ECHO_CLK[0]
For More Information On This Product,
L3_ECHO_CLK[1]
L3_ECHO_CLK[3]
Signal
{L3_DATA[16:31],
{L3_DATA[32:47],
{L3_DATA[48:63],
{L3_DATA[0:15],
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L3_ADDR[16:0]
L3_CNTL[0]
L3_CNTL[1]
L3_CLK[0]
L3_CLK[1]
t
t
L3CSKW2
L3CSKW2
L3_DP[0:1]}
L3_DP[2:3]}
L3_DP[6:7]}
L3_DP[4:5]}
Associated Echo Clock Input
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[2]
SA[16:0]
SS
SW
DQ[0:17]
K
DQ[18:35
SA[16:0]
SS
SW
DQ[0:17]
K
DQ[18:35
SRAM 0
SRAM 1
]
]
MOTOROLA
ZZ
ZZ
G
K
G
K
GND
GND
GV
GND
GND
GV
DD
DD
/2
/2