AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 25

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

The amount the parameters will increase or decrease is determined by the amount of propagation delay
added or subtracted from the trace lengths. Changes in L3_CLK and synchronization loop lengths are
independent and cumulative. It is important to note that shortening or lengthening the L3_CLK trace lengths
affects all of the parameters and always by an equal amount. For example, shortening the L3_CLK trace
lengths such that 100 ps of propagation delay is added increases the SRAM input setup and processor input
hold margins by 100 ps while simultaneously decreasing the SRAM input hold and processor input setup
margins by 100 ps. If it is desired to change only the SRAM input timing margins while leaving the
processor’s input timing margins unchanged, then an equal amount of propagation delay must be added to
the feedback loop in order to offset the effects of changing the L3_CLK trace lengths. How much actual
trace length will need to be removed or added to achieve a given change in a propagation time is design
dependent and should be determined using careful analysis and simulation of the board and trace properties.
A discussion on how to determine propagation delay is beyond the scope of this document but some
references in the bibliography discuss the topic in great detail, particularly High-Speed Digital Design: A
Handbook of Black Magic.
4.3 Adjusting AC Timing Margins for MSUG2 DDR SRAM
Adjusting AC timing margins for MSUG2 DDR is somewhat simplified because the independence of the
echo clocks from the L3 clocks allows a fair degree of flexibility in adjusting timing margins: the input
timing at the SRAM can be adjusted without affecting the input timing at the processor, and vice-versa.
Changing the length of an L3_CLK trace affects only the SRAM input setup and hold margins, while
changing the length of an L3_ECHO_CLK trace affects only the processor’s input setup and hold margins.
For the MPC7455, the L3OH bits may be useful in some cases, depending on which timing requirement is
being violated and the device revision in question, while in other cases it may not be possible to use L3OH
to correct timing problems. For the MPC7457, the L3OHCR generally provides enough granularity and
flexibility to allow adjustments to be made entirely in software without need to resort to hardware fixes in
most systems. For the MPC7450 and MPC7451, which implement neither L3OH[0–1] or the L3OHCR,
adjusting trace lengths is the only way of adjusting AC timing margins.
4.3.1 Adjusting Address, Control, and Data Write Timing
For the MPC7455, L3OH[0–1] offer the simplest method of adjusting the AC timing of the L3 interface.
Likewise, L3OHCR settings can be used for the MPC7457 to adjust output AC timing. Changing the length
of an L3 clock trace length to skew a the clock will affect the input setup and hold time margins of all signals
(data, address, and control) being received by that SRAM. Note that this does not affect the data input setup
and input hold margins for data being read from the processor because those signals are being latched by
the processor using an echo clock input.
MOTOROLA
Processor input setup margin
Processor input hold margin
Table 9. Effects of Clock Trace Lengths on AC Timing Margins for PB2 and
Parameter
Understanding the MPC7450 Family L3 Cache Hardware Interface
Freescale Semiconductor, Inc.
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Late Write SRAM (continued)
Go to: www.freescale.com
Change in L3_CLK Trace Length
(Relative to Other Signals in
Decrease
Increase
Shorten
Clock Group)
Lengthen
Decrease
Increase
Adjusting AC Timing Margins
Loop Length (Relative to Other
Change in Synchronization
Decrease
Increase
Shorten
Signals in Clock Group)
Lengthen
Decrease
Increase
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