AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 9

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

2.2 L2 Cache Control Register (L2CR)
For the MPC7455 (only), one bit in the L2CR, L3OH0 (L2CR[12]), is used to configure the L3 interface.
For
(L3OH1)—MPC7455-Specific,” and the appropriate hardware specifications for a particular device. This
bit is reserved on all MPC7450 family devices except the MPC7455.
2.3 Memory Subsystem Control Register (MSSCR0)
Two bit fields in MSSCR0, L3TCEN, and L3TC, affect the number of cycles the processor will wait before
issuing a write transaction to the SRAM following a read transaction. The MPC7457 supports an additional
bit field, L3TCEXT, that allows a longer wait period; this field is not implemented on MPC7450, MPC7451,
or MPC7455. For MSUG2 DDR, this turn around time is normally one clock, while it is two clocks for
pipelined burst and late write SRAM types. Because it may be desirable to increase this turn around time
during system debug, these defaults can be overridden in software by setting L3TCEN. When this bit is set,
the turn around time is defined by the value of the L3TC and L3TCEXT fields as shown in Table 4.
Adjusting the turn around time may also be useful in special applications where the L3 interface is used to
interface with devices other than SRAM; see Section 5.2, “Address Bus Bit Ordering and Alternative Uses
of the Backside Cache Interface,” for more information. For most applications, L3TCEN and L3TC should
normally be cleared.
MOTOROLA
Denotes Signals
Denotes Signals
Being Latched
Being Latched
MPC7455
by SRAM 1
by SRAM 0
Relative to
L3_CLK[1]
Relative to
L3_CLK[0]
Figure 6. Example Showing Effects of Setting L3OH[0-1] = 0b01 on L3 Interface Timing for
more
information
Understanding the MPC7450 Family L3 Cache Hardware Interface
Freescale Semiconductor, Inc.
on
L3_ECHO_CLK[2]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[3]
For More Information On This Product,
{L3_DATA[16:31],
this
{L3_DATA[32:47],
{L3_DATA[48:63],
{L3_DATA[0:15],
MPC7455 Rev. 2.1 and Prior
Go to: www.freescale.com
bit,
L3_ADDR[16:0]
L3_CNTL[0]
L3_CNTL[1]
L3_CLK[0]
L3_CLK[1]
see
L3_DP[0:1]}
L3_DP[2:3]}
L3_DP[4:5]}
L3_DP[6:7]}
Section 2.1.4,
Clock-to-Clock
Configuring the L3 Cache Interface in Software
Added
Skew
“L3
Output
SA[16:0]
SS
SW
DQ[0:17]
K
DQ[18:36
SA[16:0]
SS
SW
DQ[0:17]
K
DQ[18:36
SRAM 0
SRAM 1
Valid
]
]
Time
ZZ
ZZ
G
G
K
K
GND
GND
GV
GND
GND
GV
Adjust
DD
DD
/2
/2
9