AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 27

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

5 Special Considerations for the L3 Address Bus
5.1 Burst Accesses and MSUG2 DDR
When accessing pipelined burst or late write SRAM, the MPC7450 does not use the burst feature of the
SRAM. Instead, the processor issues a unique address for each beat of data. This is not possible with DDR
SRAM types, however, because address and control signals are essentially SDR inputs (that is, they are only
driven/sampled on rising clock edges). As a result, the burst feature of DDR SRAM must be used. For
MOTOROLA
L3 address and control
(at SRAM)
L3_CLK[0:1]
(at SRAM)
Data Read:
L3_DATA
(at SRAM)
L3_ECHO_CLK[0:3]
(at CPU)
Data Write, Address, and Control:
L3_DATA
(at CPU)
Figure 20. Improving Timing Margins By Adjusting the Length of Clock and Echo Clock Traces
Making the L3_ECHO_CLK trace shorter
moves the received echo clock edge in
this direction
Understanding the MPC7450 Family L3 Cache Hardware Interface
Making the L3_CLK signal trace shorter
moves the clock edge in this direction
Freescale Semiconductor, Inc.
For More Information On This Product,
Changing the echo clock trace lengths has no effect on data
write access timing or address and control timing
Go to: www.freescale.com
for DDR SRAM
Special Considerations for the L3 Address Bus
Making the L3_ECHO_CLK trace longer
moves the received echo clock edge in
this direction
Making the L3_CLK signal trace longer
moves the clock edge in this direction
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