AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 10

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Configuring the L3 Cache Interface in Software
Configuring the L3 Cache Interface in Software
1
2.4 L3 Output Hold Control Register
The MP7475 implements an entire register, L3OHCR, dedicated to controlling the output AC timing. The
function of this registers is similar to that of L3OH[0–1] in the MPC7455. However, it is much more flexible
and allows for greater control of the output timing. Each field in the L3OHCR controls the output timing of
a group of signals. Section 4.1.1, “Using L3OHCR—MPC7457-Specific,” contains examples showing how
these bit fields may be used to adjust the AC timing of the interface to correct timing violations.
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MSSCR0[L3TCEN] MSSCR0[L3TC]
L3OHCR Bits
MPC7457-specific; not implemented on MPC7450, MPC7451, or MPC7455.
0–1
2–4
5–7
(L3OHCR)—MPC7457-Specific
X
0
0
0
1
1
1
1
1
1
1
1
Understanding the MPC7450 Family L3 Cache Hardware Interface
Bit Field Name
L3CLK0_OH
L3CLK1_OH
L3AOH
0b00
0b01
0b10
0b11
0b00
0b01
0b10
0b11
Table 4. Read-to-Write Turn Around Time Settings
X
X
X
X
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5. L3OHCR Bit Field Descriptions
L3A[17:0], L3_CTRL[0:1]
MSSCR0[L3TCEXT]
Signals Affected
Go to: www.freescale.com
L3CLK0
L3CLK1
X
X
X
X
0
0
0
0
1
1
1
1
1
L3CR[L3RT]
Increases input hold time margin and decreases
input setup margin at SRAM; affects timing at both
SRAM devices
Increases input setup time margin and decreases
input hold margin at SRAM
0b00
0b01
0b10
0b11
X
X
X
X
X
X
X
X
Time (L3CLK
Turn Around
Periods)
Comment
X
1
2
2
2
3
4
5
6
7
8
9
Default for
Default for late
Reserved
Default for
MSUG2 DDR
write
pipelined burst
Settings intended
for debug use
MPC7457 only;
settings intended
for debug use
Comment
MOTOROLA