AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 7

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

These slight deviations from the ideal case are not comprehended in the L3 AC timing parameters in the
hardware specifications. However, because the L3 AC timing specifications are guard banded, devices
operating in non-integer ratio clock modes should meet all specifications. Additionally, because the amount
of delay incurred is inversely proportional to the core frequency, higher core frequencies further mitigate
any effects from it in a typical application. If, however, after a detailed AC timing analysis is completed,
there is a concern that there may be very small margins for the SRAM’s input hold, L3NIRCA can be set in
order to provide an additional VCO phase (that is, one-quarter core clock) of input hold margin at the
SRAM. Note that because this shifts the clocks, the SRAM’s input setup margin is reduced by the same
amount and this bit should not be set if input setup time margin at the SRAM is very small.
2.1.4 L3 Output Valid Time Adjust (L3OH1)—MPC7455-Specific
For the MPC7455 (Rev. 2.1 and later), L3OH1 (L3CR[12]) can be used in conjunction with L3OH0
(L2CR[12]) to provide additional output hold time from the processor. Only the MPC7455 implements these
bits and exact implementations vary according to device revision, as shown in Table 3. For MPC7455
Rev. 2.1, these bits operate by causing the L3CLK[0:1] signals to drive clock edges earlier relative to the
address, control, and data signals, similar in effect to the L2CR[L2OH] bits found on some earlier
processors such as the MPC755 and MPC7410. This has the effect of increasing the amount of input hold
time provided to the SRAM. However, it must be noted that it also causes the amount of input setup margin
at the SRAM to reduce by a like amount. For MPC7455 Rev. 3.x and later, non-zero values cause the L3
clocks to be delayed relative to the address, control, and data signals, resulting in faster output valid time
but less output hold time. It is important to note the distinction. For specific information on the effect of
these bits on the L3 AC timing, see the appropriate hardware specifications for a particular device.
MOTOROLA
internal_L3clk
Locations of L3_CLK edges if
offset exactly ¾ L3CLK period
from internal_L3clk
Figure 5. Location of L3_CLK Edges with 3.5:1 Core:L3 Ratio and L3CR[L3NIRCA] = 1
L3CLK[0:1]
L3_ADDR
L3_DATA
VCO_clk
core_clk
Understanding the MPC7450 Family L3 Cache Hardware Interface
Address 0
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
Configuring the L3 Cache Interface in Software
Address 1
Data 0
Data 1
Data 2
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