ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 18

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
POWER MANAGEMENT
The ADE7880 has four modes of operation, determined by the
state of the PM0 and PM1 pins (see Table 8). These pins provide
complete control of the ADE7880 operation and can easily be
connected to an external microprocessor I/O. The PM0 and
PM1 pins have internal pull-up resistors. See Table 10 and Table
11 for a list of actions that are recommended before and after
setting a new power mode.
Table 8. Power Supply Modes
Power Supply Modes
PSM0, Normal Power Mode
PSM1, Reduced Power Mode
PSM2, Low Power Mode
PSM3, Sleep Mode
PSM0—NORMAL POWER MODE (ALL PARTS)
In PSM0 mode, the ADE7880 is fully functional. The PM0 pin
is set to high and the PM1 pin is set to low for the ADE7880 to
enter this mode. If the ADE7880 is in PSM1, PSM2, or PSM3
mode and is switched into PSM0 mode, then all control registers
take the default values with the exception of the threshold register,
LPOILVL, which is used in PSM2 mode, and the CONFIG2
register, both of which maintain their values.
The ADE7880 signals the end of the transition period by
triggering the IRQ1 interrupt pin low and setting Bit 15
(RSTDONE) in the STATUS1 register to 1. This bit is 0 during the
transition period and becomes 1 when the transition is finished.
The status bit is cleared and the IRQ1 pin is set back to high by
writing to the STATUS1 register with the corresponding bit set
to 1. Bit 15 (RSTDONE) in the interrupt mask register does not
have any functionality attached even if the IRQ1
Bit 15 (RSTDONE) in the STATUS1 register is set to 1. This
makes the RSTDONE interrupt unmaskable.
PSM1—REDUCED POWER MODE
In the reduced power mode, PSM1, the ADE7880 measures the
mean absolute values (mav) of the 3-phase currents and stores
the results in the AIMAV, BIMAV, and CIMAV 20-bit registers.
This mode is useful in missing neutral cases in which the voltage
supply of the ADE7880 is provided by an external battery. The
serial ports, I
can be used to read the AIMAV, BIMAV, and CIMAV registers. It
is not recommended to read any of the other registers because
their values are not guaranteed in this mode. Similarly, a write
operation is not taken into account by the ADE7880 in this
mode.
In summary, in this mode, it is not recommended to access any
register other than AIMAV, BIMAV, and CIMAV. The circuit
that computes the rms estimates is also active during PSM0;
therefore, its calibration can be completed in either PSM0 mode
2
C or SPI, are enabled in this mode; the active port
PM1
0
0
1
1
pin goes low when
PM0
1
0
0
1
Rev. PrE | Page 18 of 103
or in PSM1 mode. Note that the ADE7880 does not provide any
register to store or process the corrections resulting from the
calibration process. The external microprocessor stores the gain
values in connection with these measurements and uses them
during PSM1 (see the Current Mean Absolute Value
Calculation section for more details on the xIMAV registers).
The 20-bit mean absolute value measurements done in PSM1,
although available also in PSM0, are different from the rms
measurements of phase currents and voltages executed only in
PSM0 and stored in the xIRMS and xVRMS 24-bit registers. See
the
Current Mean Absolute Value Calculation section for details.
If the ADE7880 is set in PSM1 mode after it was in the PSM0
mode, the ADE7880 immediately begins the mean absolute
value calculations without any delay. The xIMAV registers are
accessible at any time; however, if the ADE7880 is set in PSM1
mode after it was in PSM2 or PSM3 modes, the ADE7880
signals the start of the mean absolute value computations by
triggering the IRQ1
accessed only after this moment.
PSM2—LOW POWER MODE
In the low power mode, PSM2, the ADE7880 compares all
phase currents against a threshold for a period of 0.02 ×
(LPLINE[4:0] + 1) seconds, independent of the line frequency.
LPLINE[4:0] are Bits[7:3] of the LPOILVL register (see Table 9).
Table 9. LPOILVL Register
Bit
[2:0]
[7:3]
The threshold is derived from Bits[2:0] (LPOIL[2:0]) of the
LPOILVL register as LPOIL[2:0]/8 of full scale. Every time
one phase current becomes greater than the threshold, a
counter is incremented. If every phase counter remains below
LPLINE[4:0] + 1 at the end of the measurement period, then
the IRQ0 pin is triggered low. If a single phase counter becomes
greater or equal to LPLINE[4:0] + 1 at the end of the
measurement period, the
illustrates how the ADE7880 behaves in PSM2 mode when
LPLINE[4:0] = 2 and LPOIL[2:0] = 3. The test period is three
50 Hz cycles (60 ms), and the Phase A current rises above the
LPOIL[2:0] threshold three times. At the end of the test period,
the IRQ1 pin is triggered low.
Mnemonic
LPOIL[2:0]
LPLINE[4:0]
Preliminary Technical Data
pin low. The xIMAV registers can be
Default
111
00000
IRQ1 pin is triggered low.
Description
Threshold is put at a value
corresponding to full scale
multiplied by LPOIL/8.
The measurement period is
(LPLINE[4:0] + 1)/50 sec.
Figure 8