ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 62

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
The ADE7880 contains a high speed data capture (HSDC) port
that is specially designed to provide fast access to the waveform
sample registers. Read the HSDC Interface section for more
details.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
All registers listed in Table 22 are transmitted signed extended
from 24 bits to 32 bits (see Figure 19).
ENERGY-TO-FREQUENCY CONVERSION
The ADE7880 provides three frequency output pins: CF1, CF2,
and CF3. The CF2 pin is multiplexed with the HREADY pin of
the harmonic calculations block. When HREADY is enabled,
the CF2 functionality is disabled at the pin. The CF3 pin is
multiplexed with the HSCLK pin of the HSDC interface. When
HSDC is enabled, the CF3 functionality is disabled at the pin.
CF1 pin is always available. After initial calibration at
manufacturing, the manufacturer or end customer verifies the
energy meter calibration. One convenient way to verify the
meter calibration is to provide an output frequency
proportional to the active, reactive, or apparent powers under
steady load conditions. This output frequency can provide a
simple, single-wire, optically isolated interface to external
calibration equipment. Figure 62 illustrates the energy-to-
frequency conversion in the ADE7880.
The DSP computes the instantaneous values of all phase powers:
total active, fundamental active, fundamental reactive, and
apparent. The process in which the energy is sign accumulated
in various xWATTHR, xFVARHR, and xVAHR registers has
already been described in the energy calculation sections: Active
Energy Calculation, Fundamental Reactive Energy Calculation,
and Apparent Energy Calculation. In the energy-to-frequency
conversion process, the instantaneous powers generate signals
at the frequency output pins (CF1, CF2, and CF3). One digital-
to-frequency converter is used for every CFx pin. Every converter
sums certain phase powers and generates a signal proportional
to the sum. Two sets of bits decide what powers are converted.
First, Bits[2:0] (TERMSEL1[2:0]), Bits[5:3] (TERMSEL2[2:0]),
and Bits[8:6] (TERMSEL3[2:0]) of the COMPMODE register
decide which phases, or which combination of phases, are added.
The TERMSEL1 bits refer to the CF1 pin, the TERMSEL2 bits
refer to the CF2 pin, and the TERMSEL3 bits refer to the CF3
pin. The TERMSELx[0] bits manage Phase A. When set to 1,
Phase A power is included in the sum of powers at the CFx
converter. When cleared to 0, Phase A power is not included.
The TERMSELx[1] bits manage Phase B, and the TERMSELx[2]
bits manage Phase C. Setting all TERMSELx bits to 1 means all
3-phase powers are added at the CFx converter. Clearing all
TERMSELx bits to 0 means no phase power is added and no
CF pulse is generated.
Rev. PrE | Page 62 of 103
Second, Bits[2:0] (CF1SEL[2:0]), Bits[5:3] (CF2SEL[2:0]), and
Bits[8:6] (CF3SEL[2:0]) in the CFMODE register decide what
type of power is used at the inputs of the CF1, CF2, and CF3
converters, respectively. Table 23 shows the values that CFxSEL
can have: total active, apparent, fundamental active, or
fundamental reactive powers.
Table 23. CFxSEL Bits Description
CFxSEL
000
001
010
011
100
101 to
111
By default, the TERMSELx bits are all 1 and the CF1SEL bits are
000, the CF2SEL bits are 100, and the CF3SEL bits are 010. This
means that by default, the CF1 digital-to-frequency converter
produces signals proportional to the sum of all 3-phase total
active powers, CF2 produces signals proportional to
fundamental reactive powers, and CF3 produces signals
proportional to apparent powers.
Similar to the energy accumulation process, the energy-to-
frequency conversion is accomplished in two stages. The first
stage is the same stage illustrated in the energy accumulation
sections of active, reactive and apparent powers (See Active
Energy Calculation, Fundamental Reactive Energy Calculation,
Apparent Energy Calculation sections). The second stage
consists of the frequency divider by the CFxDEN 16-bit
unsigned registers. The values of CFxDEN depend on the meter
constant (MC), measured in impulses/kWh and how much
energy is assigned to one LSB of various energy registers:
xWATTHR, xFVARHR, and so forth. Suppose a derivative of
wh [10
as one LSB of xWATTHR register. Then, CFxDEN is as follows:
The derivative of wh must be chosen in such a way to obtain a
CFxDEN register content greater than 1. If CFxDEN = 1, then
the CFx pin stays active low for only 1 µs. Thus, CFxDEN
register should not be set to 1. The frequency converter cannot
accommodate fractional results; the result of the division must be
CFxDEN
n
wh] where n is a positive or negative integer, is desired
Description
CFx signal proportional to the
sum of total phase active
powers
Reserved
CFx signal proportional to the
sum of phase apparent powers
CFx signal proportional to the
sum of fundamental phase
active powers
CFx signal proportional to the
sum of fundamental phase
reactive powers
Reserved
=
MC
Preliminary Technical Data
[
imp/kwh
10
3
]
×
10
n
Registers
Latched When
CFxLATCH = 1
AWATTHR,
BWATTHR,
CWATTHR
AVAHR, BVAHR,
CVAHR
AFWATTHR,
BFWATTHR,
CFWATTHR
AFVARHR,
BFVARHR,
CFVARHR
(46)