ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 73

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
leaves the accessed register in a state that cannot be guaranteed,
every time a register is written, its value should be verified by
reading it back. The protocol is similar to the protocol used in
I
SPI Read Operation
The read operation using the SPI interface of the ADE7880
initiate when the master sets the SS/HSA pin low and begins
sending one byte, representing the address of the ADE7880, on
the MOSI line. The master sets data on the MOSI line starting
SPI Read Operation of Harmonic Calculations Registers
The registers containing the harmonic calculation results are
located starting at address 0xE880 and are all 32-bit width. They
can be read in two ways: one is the regular way, one register at a
time (see SPI Read Operation section for details) and the other
2
C interface.
Figure 78. Connecting ADE7880 SPI with an SPI Device
ADE7880
SCLK
MOSI
MISO
SS
SCLK
MOSI
MISO
SS\
0
MOSI
MISO
SCK
SCLK
SS\
MOSI
MISO
0 0
Figure 80. SPI Read Operation of n 32-Bit harmonic calculations registers
SS
device
0
SPI
0
Figure 79. SPI Read Operation of a 32-Bit Register
0 0 0
0
0
0
0 0 0
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1
1
Reg Address
15 14
REGISTER ADDRESS
with the first high-to-low transition of SCLK. The SPI of the
ADE7880 samples data on the low-to-high transitions of SCLK.
The most significant seven bits of the address byte can have any
value, but as a good programming practice, they should be
different from 0111000b, the seven bits used in the I
Bit 0 (read/write) of the address byte must be 1 for a read
operation. Next, the master sends the 16-bit address of the
register that is read. After the ADE7880 receives the last bit of
address of the register on a low-to-high transition of SCLK, it
begins to transmit its contents on the MISO line when the next
SCLK high-to-low transition occurs; thus, the master can
sample the data on a low-to-high SCLK transition. After the
master receives the last bit, it sets the SS and SCLK lines high
and the communication ends. The data lines, MOSI and MISO,
go into a high impedance state. See Figure 79 for details of the
SPI read operation.
way is reading multiple consecutive registers at a time in a burst
mode. The burst mode initiates when the master sets the SS
/HSA pin low and begins sending one byte, representing the
address of the ADE7880, on the MOSI line. The address is the
same address byte used for reading only one register. The
master sets data on the MOSI line starting with the first high-
1 0
31 30
31
Reg 0 Value
REGISTER VALUE
1 0
0
31
Reg n Value
0
ADE7880
2
C protocol.