ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 93

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Bit
Location
31:26
Table 37. PHSTATUS Register (Address 0xE600)
Bit
Location
2:0
3
4
5
8:6
9
10
11
12
13
14
15
Table 38. PHNOLOAD Register (Address 0xE608)
Bit
Location
0
1
2
3
4
5
6
Bit Mnemonic
Reserved
Bit Mnemonic
Reserved
OIPHASE[0]
OIPHASE[1]
OIPHASE[2]
Reserved
OVPHASE[0]
OVPHASE[1]
OVPHASE[2]
VSPHASE[0]
VSPHASE[1]
VSPHASE[2]
Reserved
Bit Mnemonic
NLPHASE[0]
NLPHASE[1]
NLPHASE[2]
FNLPHASE[0]
FNLPHASE[1]
FNLPHASE[2]
VANLPHASE[0]
Default Value
000 0000
Default Value
000
0
0
0
000
0
0
0
0
0
0
0
Default Value
0
0
0
0
0
0
0
Description
Reserved. These bits do not manage any functionality.
Description
Reserved. These bits are always 0.
When this bit is set to 1, Phase A current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, Phase B current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, Phase C current generates Bit 17 (OI) in the STATUS1 register.
Reserved. These bits are always 0.
When this bit is set to 1, Phase A voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase B voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase C voltage generates Bit 18 (OV) in the STATUS1 register.
0: Phase A voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase A voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, phase A voltage generates Bit 16 (SAG) in
the STATUS1 register.
0: Phase B voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase B voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, phase B voltage generates Bit 16 (SAG) in
the STATUS1 register.
0: Phase C voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase C voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, phase C voltage generates Bit16 (SAG) in
the STATUS1 register.
Reserved. This bit is always 0.
Description
0: Phase A is out of no load condition determined by phase A total active power and
apparent power.
1: Phase A is in no load condition determined by phase A total active power and apparent
power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
0: Phase B is out of no load condition determined by phase B total active power and
apparent power.
1: Phase B is in no load condition determined by phase B total active power and apparent
power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
0: Phase C is out of no load condition determined by phase C total active power and
apparent power.
1: Phase C is in no load condition determined by phase C total active power and apparent
power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
0: Phase A is out of no load condition based on fundamental active/reactive powers.
1: Phase A is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
0: Phase B is out of no load condition based on fundamental active/reactive powers.
1: Phase B is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
0: Phase C is out of no load condition based on fundamental active/reactive powers.
1: Phase C is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
0: Phase A is out of no load condition based on apparent power.
Rev. PrE| Page 93 of 103
ADE7880