ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 66

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
in the same moment in which a high-to-low transition at the
CF3, CF2, and CF1 pin, respectively, occurs.
Bit 8, Bit 7, and Bit 3 (SUM3SIGN, SUM2SIGN, and SUM1SIGN,
respectively) of the PHSIGN register are set in the same moment
with Bit REVPSUM3, Bit REVPSUM2, and Bit EVPSUM1 and
indicate the sign of the sum of phase powers. When cleared to
0, the sum is positive. When set to 1, the sum is negative.
Interrupts attached to Bit 18, Bit 13, and Bit 9 (REVPSUM3,
REVPSUM2, and REVPSUM1, respectively) in the STATUS0
register are enabled by setting Bit 18, Bit 13, and Bit 9 in the
MASK0 register. If enabled, the IRQ0 pin is set low, and the
status bit is set to 1 whenever a change of sign occurs. To find
the phase that triggered the interrupt, the PHSIGN register is
read immediately after reading the STATUS0 register. Next, the
status bit is cleared, and the
to the STATUS0 register with the corresponding bit set to 1.
NO LOAD CONDITION
The no load condition is defined in metering equipment standards
as occurring when the voltage is applied to the meter and no cur-
rent flows in the current circuit. To eliminate any creep effects in
the meter, the ADE7880 contains three separate no load
detection circuits: one related to the total active power, one
related to the fundamental active and reactive powers, and one
related to the apparent powers.
No Load Detection Based On Total Active Power and
Apparent Power
This no load condition uses the total active energy and the
apparent energy (see Apparent Power Calculation section for
details) to trigger this no load condition. The apparent energy is
proportional to the rms values of the corresponding phase
current and voltage. If neither total active energy nor apparent
energy are accumulated for a time indicated in the respective
APNOLOAD and VANOLOAD unsigned 16-bit registers, the
no load condition is triggered, the total active energy of that
phase is not accumulated and no CFx pulses are generated
based on the total active energy.
The expression used to compute APNOLOAD and
VANOLOAD unsigned 16-bit values is
where:
Y is the required no load current threshold computed relative to
full scale. For example, if the no load threshold current is set
10,000 times lower than full scale value, then Y=10,000.
WTHR and VATHR represent values stored in the WTHR and
VATHR registers and are used as the thresholds in the first stage
VANOLOAD
APNOLOAD
=
=
2
2
16
16
−
−
Y
IRQ0 pin is set high again by writing
Y
×
×
VATHR
WTHR
PMAX
PMAX
×
×
2
2
17
17
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(47)
energy accumulators for active and apparent energy
respectively (see Active Energy Calculation section)
PMAX=27,059,678=0x19CE5DE, the instantaneous active
power computed when the ADC inputs are at full scale.
The VANOLOAD register usually contains the same value as
the APNOLOAD register. When APNOLOAD and VANOLOAD
are set to 0x0, the no load detection circuit is disabled. If only
VANOLOAD is set to 0, then the no load condition is triggered
based only on the total active power being lower than
APNOLOAD. In the same way, if only APNOLOAD is set to 0x0,
the no load condition is triggered based only on the apparent
power being lower than VANOLOAD.
Bit 0 (NLOAD) in the STATUS1 register is set when a no load
condition in one of the three phases is triggered. Bits[2:0]
(NLPHASE[2:0]) in the PHNOLOAD register indicate the state
of all phases relative to a no load condition and are set simulta-
neously with Bit NLOAD in the STATUS1 register. NLPHASE[0]
indicates the state of Phase A, NLPHASE[1] indicates the state
of Phase B, and NLPHASE[2] indicates the state of Phase C.
When Bit NLPHASE[x] is cleared to 0, it means the phase is out
of a no load condition. When set to 1, it means the phase is in a
no load condition.
An interrupt attached to Bit 0 (NLOAD) in the STATUS1
register can be enabled by setting Bit 0 in the MASK1 register.
If enabled, the IRQ1 pin is set to low, and the status bit is set
to 1 whenever one of three phases enters or exits this no load
condition. To find the phase that triggered the interrupt, the
PHNOLOAD register is read immediately after reading the
STATUS1 register. Next, the status bit is cleared, and the
pin is set to high by writing to the STATUS1 register with the
corresponding bit set to 1.
No Load Detection Based on Fundamental Active and
Reactive Powers
This no load condition is triggered when no less significant bits
are accumulated into the fundamental active and reactive
energy registers on one phase (xFWATTHR and xFVARHR,
x=A, B or C) for a time indicated in the respective APNOLOAD
and VARNOLOAD unsigned 16-bit registers. In this case, the
fundamental active and reactive energies of that phase are not
accumulated and no CFx pulses are generated based on these
energies. APNOLOAD is the same no load threshold set for the
total active and VNOM based apparent powers. The
VARNOLOAD register usually contains the same value as the
APNOLOAD register. If only APNOLOAD is set to 0x0, then the
fundamental active power is accumulated without restriction. In
the same way, if only VARNOLOAD is set to 0x0, the fundamental
reactive power is accumulated without restriction.
Bit 1 (FNLOAD) in the STATUS1 register is set when this no
load condition in one of the three phases is triggered. Bits[5:3]
(FNLPHASE[2:0]) in the PHNOLOAD register indicate the
Preliminary Technical Data
IRQ1