ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 72

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
I
The registers containing the harmonic calculation results are
located starting at address 0xE880 and are all 32-bit width. They
can be read in two ways: one is the regular way, one register at a
time (see I2C Read Operation section for details) and the other
way is reading multiple consecutive registers at a time in a burst
mode. This burst mode is accomplished in two stages. As seen
in Figure 77, the first stage sets the pointer to the address of the
register and is identical to the first stage executed when only
one register is read. The second stage reads the content of the
registers. The second stage begins with the master generating a
new start condition followed by an address byte equal to the
address byte used when one single register is read, 0x71. After
this byte is received, the ADE7880 generates an acknowledge.
Then, the ADE7880 sends the value of the first register located
at the pointer, and after every eight bits are received, the master
generates an acknowledge. All the bytes are sent with the most
significant bit first. After the bytes of the first register are sent, if
the master acknowledges the last byte, the ADE7880 increments
the pointer by 1 location to position it at the next register and
begins to send it out byte by byte, most significant bit first. If
the master acknowledges the last byte, the ADE7880 increments
the pointer again and begins to send data from the next register.
The process continues until the master ceases to generate an
acknowledge at the last byte of the register and then generates a
stop condition. It is recommended to not allow locations
greater then 0xE89F, the last location of the harmonic
calculations registers.
2
C Read Operation of Harmonic Calculations Registers
S
A
R
S 0 1 1 1 0 0 0
S
A
R
S
T
T
T
T
0 1 1 1 0 0 0
slave address
slave address
ACK generated by
ADE7880
0
1
A
C
K
A
C
K
15
31
Byte3 (MS) of reg 0
MS 8 bits of reg
address
Figure 77.i
ACK generated by
2
CRead Operation of n 32-Bit harmonic calculations registers
16
ADE7880
8
A
C
K
A
C
K
7
LS 8 bits of reg
Rev. PrE | Page 72 of 103
7
address
Byte0 (LS) of reg 0
ACK generated by
0
Master
SPI-Compatible Interface
The SPI of the ADE7880 is always a slave of the communication
and consists of four pins (with dual functions): SCLK/SCL,
MOSI/SDA, MISO/HSD, and SS/HSA. The functions used in
the SPI-compatible interface are SCLK, MOSI, MISO, and
The serial clock for a data transfer is applied at the SCLK logic
input. This logic input has a Schmitt trigger input structure that
allows the use of slow rising (and falling) clock edges. All data
transfer operations synchronize to the serial clock. Data shifts
into the ADE7880 at the MOSI logic input on the falling edge of
SCLK and the ADE7880 samples it on the rising edge of SCLK.
Data shifts out of the ADE7880 at the MISO logic output on a
falling edge of SCLK and can be sampled by the master device
on the raising edge of SCLK. The most significant bit of the
word is shifted in and out first. The maximum serial clock
frequency supported by this interface is 2.5 MHz. MISO stays in
high impedance when no data is transmitted from the
ADE7880. See
the ADE7880 SPI and a master device containing an SPI
interface.
The SS logic input is the chip select input. This input is used
when multiple devices share the serial bus. Drive the SS input
low for the entire data transfer operation. Bringing SS high
during a data transfer operation aborts the transfer and places
the serial bus in a high impedance state. A new transfer can
then be initiated by returning the
However, because aborting a data transfer before completion
A
C
K
0
A
C
K
7
Byte3 (LS) of reg 1
Figure 78
Preliminary Technical Data
for details of the connection between
0
A
C
K
SS logic input to low.
7
Byte0 (LS) of reg n
0
SS.
N
O
A
C
K
S
O
P
S
T